72f4ec2cf54970b409476e14a2c31db1d30c5713
[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Support.asm
1 //------------------------------------------------------------------------------
2 //
3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
4 //
5 // All rights reserved. This program and the accompanying materials
6 // are licensed and made available under the terms and conditions of the BSD License
7 // which accompanies this distribution. The full text of the license may be found at
8 // http://opensource.org/licenses/bsd-license.php
9 //
10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 //
13 //------------------------------------------------------------------------------
14
15 EXPORT ArmInvalidateInstructionCache
16 EXPORT ArmInvalidateDataCacheEntryByMVA
17 EXPORT ArmCleanDataCacheEntryByMVA
18 EXPORT ArmCleanInvalidateDataCacheEntryByMVA
19 EXPORT ArmInvalidateDataCacheEntryBySetWay
20 EXPORT ArmCleanDataCacheEntryBySetWay
21 EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
22 EXPORT ArmDrainWriteBuffer
23 EXPORT ArmEnableMmu
24 EXPORT ArmDisableMmu
25 EXPORT ArmMmuEnabled
26 EXPORT ArmEnableDataCache
27 EXPORT ArmDisableDataCache
28 EXPORT ArmEnableInstructionCache
29 EXPORT ArmDisableInstructionCache
30 EXPORT ArmEnableBranchPrediction
31 EXPORT ArmDisableBranchPrediction
32 EXPORT ArmV7AllDataCachesOperation
33 EXPORT ArmDataMemoryBarrier
34 EXPORT ArmDataSyncronizationBarrier
35 EXPORT ArmInstructionSynchronizationBarrier
36
37 AREA ArmCacheLib, CODE, READONLY
38 PRESERVE8
39
40 DC_ON EQU ( 0x1:SHL:2 )
41 IC_ON EQU ( 0x1:SHL:12 )
42
43
44
45 ArmInvalidateDataCacheEntryByMVA
46 mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
47 dsb
48 isb
49 bx lr
50
51
52 ArmCleanDataCacheEntryByMVA
53 mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
54 dsb
55 isb
56 bx lr
57
58
59 ArmCleanInvalidateDataCacheEntryByMVA
60 mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
61 dsb
62 isb
63 bx lr
64
65
66 ArmInvalidateDataCacheEntryBySetWay
67 mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
68 dsb
69 isb
70 bx lr
71
72
73 ArmCleanInvalidateDataCacheEntryBySetWay
74 mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
75 dsb
76 isb
77 bx lr
78
79
80 ArmCleanDataCacheEntryBySetWay
81 mcr p15, 0, r0, c7, c10, 2 ; Clean this line
82 dsb
83 isb
84 bx lr
85
86
87 ArmDrainWriteBuffer
88 mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
89 dsb
90 isb
91 bx lr
92
93
94 ArmInvalidateInstructionCache
95 mov R0,#0
96 mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
97 mov R0,#0
98 dsb
99 isb
100 bx LR
101
102 ArmEnableMmu
103 mrc p15,0,R0,c1,c0,0
104 orr R0,R0,#1
105 mcr p15,0,R0,c1,c0,0
106 dsb
107 isb
108 bx LR
109
110 ArmMmuEnabled
111 mrc p15,0,R0,c1,c0,0
112 and R0,R0,#1
113 isb
114 bx LR
115
116 ArmDisableMmu
117 mov R0,#0
118 mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU
119 mrc p15,0,R0,c1,c0,0
120 bic R0,R0,#1
121 mcr p15,0,R0,c1,c0,0 ;Disable MMU
122 dsb
123 isb
124 bx LR
125
126 ArmEnableDataCache
127 ldr R1,=DC_ON
128 mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
129 orr R0,R0,R1 ;Set C bit
130 mcr p15,0,r0,c1,c0,0 ;Write control register configuration data
131 dsb
132 isb
133 bx LR
134
135 ArmDisableDataCache
136 ldr R1,=DC_ON
137 mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
138 bic R0,R0,R1 ;Clear C bit
139 mcr p15,0,r0,c1,c0,0 ;Write control register configuration data
140 isb
141 bx LR
142
143 ArmEnableInstructionCache
144 ldr R1,=IC_ON
145 mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
146 orr R0,R0,R1 ;Set I bit
147 mcr p15,0,r0,c1,c0,0 ;Write control register configuration data
148 dsb
149 isb
150 bx LR
151
152 ArmDisableInstructionCache
153 ldr R1,=IC_ON
154 mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
155 BIC R0,R0,R1 ;Clear I bit.
156 mcr p15,0,r0,c1,c0,0 ;Write control register configuration data
157 isb
158 bx LR
159
160 ArmEnableBranchPrediction
161 mrc p15, 0, r0, c1, c0, 0
162 orr r0, r0, #0x00000800
163 mcr p15, 0, r0, c1, c0, 0
164 isb
165 bx LR
166
167 ArmDisableBranchPrediction
168 mrc p15, 0, r0, c1, c0, 0
169 bic r0, r0, #0x00000800
170 mcr p15, 0, r0, c1, c0, 0
171 isb
172 bx LR
173
174
175 ArmV7AllDataCachesOperation
176 stmfd SP!,{r4-r12, LR}
177 mov R1, R0 ; Save Function call in R1
178 mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
179 ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
180 mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
181 beq Finished
182 mov R10, #0
183
184 Loop1
185 add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
186 mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
187 and R12, R12, #7 ; get those 3 bits alone
188 cmp R12, #2
189 blt Skip ; no cache or only instruction cache at this level
190 mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
191 isb ; isb to sync the change to the CacheSizeID reg
192 mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
193 and R2, R12, #&7 ; extract the line length field
194 add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
195 ldr R4, =0x3FF
196 ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
197 clz R5, R4 ; R5 is the bit position of the way size increment
198 ldr R7, =0x00007FFF
199 ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
200
201 Loop2
202 mov R9, R4 ; R9 working copy of the max way size (right aligned)
203
204 Loop3
205 orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
206 orr R0, R0, R7, LSL R2 ; factor in the index number
207
208 blx R1
209
210 subs R9, R9, #1 ; decrement the way number
211 bge Loop3
212 subs R7, R7, #1 ; decrement the index
213 bge Loop2
214 Skip
215 add R10, R10, #2 ; increment the cache number
216 cmp R3, R10
217 bgt Loop1
218
219 Finished
220 ldmfd SP!, {r4-r12, lr}
221 bx LR
222
223
224 ArmDataMemoryBarrier
225 dmb
226 bx LR
227
228 ArmDataSyncronizationBarrier
229 dsb
230 bx LR
231
232 ArmInstructionSynchronizationBarrier
233 isb
234 bx LR
235
236 END