1 //------------------------------------------------------------------------------
3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
5 // All rights reserved. This program and the accompanying materials
6 // are licensed and made available under the terms and conditions of the BSD License
7 // which accompanies this distribution. The full text of the license may be found at
8 // http://opensource.org/licenses/bsd-license.php
10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 //------------------------------------------------------------------------------
15 EXPORT ArmInvalidateInstructionCache
16 EXPORT ArmInvalidateDataCacheEntryByMVA
17 EXPORT ArmCleanDataCacheEntryByMVA
18 EXPORT ArmCleanInvalidateDataCacheEntryByMVA
19 EXPORT ArmInvalidateDataCacheEntryBySetWay
20 EXPORT ArmCleanDataCacheEntryBySetWay
21 EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
22 EXPORT ArmDrainWriteBuffer
26 EXPORT ArmEnableDataCache
27 EXPORT ArmDisableDataCache
28 EXPORT ArmEnableInstructionCache
29 EXPORT ArmDisableInstructionCache
30 EXPORT ArmEnableBranchPrediction
31 EXPORT ArmDisableBranchPrediction
33 DC_ON EQU ( 0x1:SHL:2 )
34 IC_ON EQU ( 0x1:SHL:12 )
35 XP_ON EQU ( 0x1:SHL:23 )
38 AREA ArmCacheLib, CODE, READONLY
42 ArmInvalidateDataCacheEntryByMVA
45 MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
51 ArmCleanDataCacheEntryByMVA
54 MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
60 ArmCleanInvalidateDataCacheEntryByMVA
63 MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
69 ArmInvalidateDataCacheEntryBySetWay
72 mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
78 ArmCleanInvalidateDataCacheEntryBySetWay
81 mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
87 ArmCleanDataCacheEntryBySetWay
90 mcr p15, 0, r0, c7, c10, 2 ; Clean this line
99 mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
105 ArmInvalidateInstructionCache
109 MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
111 MCR p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
139 mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU
142 mcr p15,0,R0,c1,c0,0 ;Disable MMU
144 mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
146 mcr p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
155 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
156 ORR R0,R0,R1 ;Set C bit
157 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
166 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
167 BIC R0,R0,R1 ;Clear C bit
168 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
173 ArmEnableInstructionCache
177 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
178 ORR R0,R0,R1 ;Set I bit
179 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
184 ArmDisableInstructionCache
188 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
189 BIC R0,R0,R1 ;Clear I bit.
190 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
195 ArmEnableBranchPrediction
198 mrc p15, 0, r0, c1, c0, 0
199 orr r0, r0, #0x00000800
200 mcr p15, 0, r0, c1, c0, 0
205 ArmDisableBranchPrediction
208 mrc p15, 0, r0, c1, c0, 0
209 bic r0, r0, #0x00000800
210 mcr p15, 0, r0, c1, c0, 0