1 //------------------------------------------------------------------------------
3 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
4 // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
6 // This program and the accompanying materials
7 // are licensed and made available under the terms and conditions of the BSD License
8 // which accompanies this distribution. The full text of the license may be found at
9 // http://opensource.org/licenses/bsd-license.php
11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 //------------------------------------------------------------------------------
16 EXPORT ArmInvalidateInstructionCache
17 EXPORT ArmInvalidateDataCacheEntryByMVA
18 EXPORT ArmCleanDataCacheEntryByMVA
19 EXPORT ArmCleanInvalidateDataCacheEntryByMVA
20 EXPORT ArmInvalidateDataCacheEntryBySetWay
21 EXPORT ArmCleanDataCacheEntryBySetWay
22 EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
23 EXPORT ArmDrainWriteBuffer
26 EXPORT ArmDisableCachesAndMmu
28 EXPORT ArmEnableDataCache
29 EXPORT ArmDisableDataCache
30 EXPORT ArmEnableInstructionCache
31 EXPORT ArmDisableInstructionCache
32 EXPORT ArmEnableSWPInstruction
33 EXPORT ArmEnableBranchPrediction
34 EXPORT ArmDisableBranchPrediction
35 EXPORT ArmSetLowVectors
36 EXPORT ArmSetHighVectors
37 EXPORT ArmV7AllDataCachesOperation
38 EXPORT ArmDataMemoryBarrier
39 EXPORT ArmDataSynchronizationBarrier
40 EXPORT ArmInstructionSynchronizationBarrier
47 EXPORT ArmReadTpidrurw
48 EXPORT ArmWriteTpidrurw
49 EXPORT ArmIsArchTimerImplemented
52 AREA ArmV7Support, CODE, READONLY
55 DC_ON EQU ( 0x1:SHL:2 )
56 IC_ON EQU ( 0x1:SHL:12 )
57 CTRL_M_BIT EQU (1 << 0)
58 CTRL_C_BIT EQU (1 << 2)
59 CTRL_B_BIT EQU (1 << 7)
60 CTRL_I_BIT EQU (1 << 12)
63 ArmInvalidateDataCacheEntryByMVA
64 mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
69 ArmCleanDataCacheEntryByMVA
70 mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
76 ArmCleanInvalidateDataCacheEntryByMVA
77 mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
83 ArmInvalidateDataCacheEntryBySetWay
84 mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
90 ArmCleanInvalidateDataCacheEntryBySetWay
91 mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
97 ArmCleanDataCacheEntryBySetWay
98 mcr p15, 0, r0, c7, c10, 2 ; Clean this line
104 ArmInvalidateInstructionCache
105 mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
110 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
111 orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
112 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
118 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
119 bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
120 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
122 mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
123 mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
128 ArmDisableCachesAndMmu
129 mrc p15, 0, r0, c1, c0, 0 ; Get control register
130 bic r0, r0, #CTRL_M_BIT ; Disable MMU
131 bic r0, r0, #CTRL_C_BIT ; Disable D Cache
132 bic r0, r0, #CTRL_I_BIT ; Disable I Cache
133 mcr p15, 0, r0, c1, c0, 0 ; Write control register
139 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
144 ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
145 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
146 orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
147 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
153 ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
154 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
155 bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
156 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
161 ArmEnableInstructionCache
162 ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
163 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
164 orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled
165 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
170 ArmDisableInstructionCache
171 ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
172 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
173 BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled
174 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
178 ArmEnableSWPInstruction
179 mrc p15, 0, r0, c1, c0, 0
180 orr r0, r0, #0x00000400
181 mcr p15, 0, r0, c1, c0, 0
185 ArmEnableBranchPrediction
186 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
187 orr r0, r0, #0x00000800 ;
188 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
193 ArmDisableBranchPrediction
194 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
195 bic r0, r0, #0x00000800 ;
196 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
202 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
203 bic r0, r0, #0x00002000 ; clear V bit
204 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
209 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
210 orr r0, r0, #0x00002000 ; Set V bit
211 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
215 ArmV7AllDataCachesOperation
216 stmfd SP!,{r4-r12, LR}
217 mov R1, R0 ; Save Function call in R1
218 mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
219 ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
220 mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
225 add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
226 mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
227 and R12, R12, #7 ; get those 3 bits alone
229 blt Skip ; no cache or only instruction cache at this level
230 mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
231 isb ; isb to sync the change to the CacheSizeID reg
232 mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
233 and R2, R12, #&7 ; extract the line length field
234 add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
236 ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
237 clz R5, R4 ; R5 is the bit position of the way size increment
239 ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
242 mov R9, R4 ; R9 working copy of the max way size (right aligned)
245 orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
246 orr R0, R0, R7, LSL R2 ; factor in the index number
250 subs R9, R9, #1 ; decrement the way number
252 subs R7, R7, #1 ; decrement the index
255 add R10, R10, #2 ; increment the cache number
261 ldmfd SP!, {r4-r12, lr}
268 ArmDataSynchronizationBarrier
273 ArmInstructionSynchronizationBarrier
278 // Set the Address of the Vector Table in the VBAR register
279 mrc p15, 0, r0, c12, c0, 0
283 // Set the Address of the Vector Table in the VBAR register
284 mcr p15, 0, r0, c12, c0, 0
285 // Ensure the SCTLR.V bit is clear
286 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
287 bic r0, r0, #0x00002000 ; clear V bit
288 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
293 // Read CPACR (Coprocessor Access Control Register)
294 mrc p15, 0, r0, c1, c0, 2
295 // Enable VPF access (Full Access to CP10, CP11) (V* instructions)
296 orr r0, r0, #0x00f00000
297 // Write back CPACR (Coprocessor Access Control Register)
298 mcr p15, 0, r0, c1, c0, 2
300 // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
302 mcr p10,#0x7,r0,c8,c0,#0
309 //Note: Return 0 in Uniprocessor implementation
311 mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
315 mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
319 mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW
323 mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW
326 ArmIsArchTimerImplemented
327 mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1
328 and r0, r0, #0x000F0000
332 mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register