ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
   4 //
   5 // All rights reserved. This program and the accompanying materials
   6 // are licensed and made available under the terms and conditions of the BSD License
   7 // which accompanies this distribution.  The full text of the license may be found at
   8 // http://opensource.org/licenses/bsd-license.php
   9 //
  10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 //
  13 //------------------------------------------------------------------------------
  14
  15     EXPORT  ArmInvalidateInstructionCache
  16     EXPORT  ArmInvalidateDataCacheEntryByMVA
  17     EXPORT  ArmCleanDataCacheEntryByMVA
  18     EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
  19     EXPORT  ArmInvalidateDataCacheEntryBySetWay
  20     EXPORT  ArmCleanDataCacheEntryBySetWay
  21     EXPORT  ArmCleanInvalidateDataCacheEntryBySetWay
  22     EXPORT  ArmDrainWriteBuffer
  23     EXPORT  ArmEnableMmu
  24     EXPORT  ArmDisableMmu
  25     EXPORT  ArmMmuEnabled
  26     EXPORT  ArmEnableDataCache
  27     EXPORT  ArmDisableDataCache
  28     EXPORT  ArmEnableInstructionCache
  29     EXPORT  ArmDisableInstructionCache
  30     EXPORT  ArmEnableBranchPrediction
  31     EXPORT  ArmDisableBranchPrediction
  32     EXPORT  ArmV7AllDataCachesOperation
  33     EXPORT  ArmDataMemoryBarrier
  34     EXPORT  ArmDataSyncronizationBarrier
  35     EXPORT  ArmInstructionSynchronizationBarrier
  36
  37
  38 DC_ON       EQU     ( 0x1:SHL:2 )
  39 IC_ON       EQU     ( 0x1:SHL:12 )
  40
  41
  42     AREA    ArmCacheLib, CODE, READONLY
  43     PRESERVE8
  44
  45
  46 ArmInvalidateDataCacheEntryByMVA
  47   MCR     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line
  48   DSB
  49   ISB
  50   BX      lr
  51
  52
  53 ArmCleanDataCacheEntryByMVA
  54   MCR     p15, 0, r0, c7, c10, 1  ; clean single data cache line
  55   DSB
  56   ISB
  57   BX      lr
  58
  59
  60 ArmCleanInvalidateDataCacheEntryByMVA
  61   MCR     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  62   DSB
  63   ISB
  64   BX      lr
  65
  66
  67 ArmInvalidateDataCacheEntryBySetWay
  68   mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line
  69   DSB
  70   ISB
  71   bx      lr
  72
  73
  74 ArmCleanInvalidateDataCacheEntryBySetWay
  75   mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line
  76   DSB
  77   ISB
  78   bx      lr
  79
  80
  81 ArmCleanDataCacheEntryBySetWay
  82   mcr     p15, 0, r0, c7, c10, 2       ; Clean this line
  83   DSB
  84   ISB
  85   bx      lr
  86
  87
  88 ArmDrainWriteBuffer
  89   mcr     p15, 0, r0, c7, c10, 4       ; Drain write buffer for sync
  90   DSB
  91   ISB
  92   bx      lr
  93
  94
  95 ArmInvalidateInstructionCache
  96   MOV     R0,#0
  97   MCR     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
  98   MOV     R0,#0
  99   MCR     p15,0,R0,c7,c5,4      ;Instruction synchronization barrier
 100   DSB
 101   ISB
 102   BX      LR
 103
 104 ArmEnableMmu
 105   mrc     p15,0,R0,c1,c0,0
 106   orr     R0,R0,#1
 107   mcr     p15,0,R0,c1,c0,0
 108   DSB
 109   ISB
 110   bx      LR
 111
 112 ArmMmuEnabled
 113   mrc     p15,0,R0,c1,c0,0
 114   and     R0,R0,#1
 115   ISB
 116   bx      LR
 117
 118 ArmDisableMmu
 119   mov     R0,#0
 120   mcr     p15,0,R0,c13,c0,0     ;FCSE PID register must be cleared before disabling MMU
 121   mrc     p15,0,R0,c1,c0,0
 122   bic     R0,R0,#1
 123   mcr     p15,0,R0,c1,c0,0      ;Disable MMU
 124   DSB
 125   ISB
 126   bx      LR
 127
 128 ArmEnableDataCache
 129   LDR     R1,=DC_ON
 130   MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
 131   ORR     R0,R0,R1              ;Set C bit
 132   MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
 133   DSB
 134   ISB
 135   BX      LR
 136
 137 ArmDisableDataCache
 138   LDR     R1,=DC_ON
 139   MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
 140   BIC     R0,R0,R1              ;Clear C bit
 141   MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
 142   ISB
 143   BX      LR
 144
 145 ArmEnableInstructionCache
 146   LDR     R1,=IC_ON
 147   MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
 148   ORR     R0,R0,R1              ;Set I bit
 149   MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
 150   ISB
 151   BX      LR
 152
 153 ArmDisableInstructionCache
 154   LDR     R1,=IC_ON
 155   MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
 156   BIC     R0,R0,R1             ;Clear I bit.
 157   MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
 158   ISB
 159   BX      LR
 160
 161 ArmEnableBranchPrediction
 162   mrc     p15, 0, r0, c1, c0, 0
 163   orr     r0, r0, #0x00000800
 164   mcr     p15, 0, r0, c1, c0, 0
 165   ISB
 166   bx      LR
 167
 168 ArmDisableBranchPrediction
 169   mrc     p15, 0, r0, c1, c0, 0
 170   bic     r0, r0, #0x00000800
 171   mcr     p15, 0, r0, c1, c0, 0
 172   ISB
 173   bx      LR
 174
 175
 176 ArmV7AllDataCachesOperation
 177   STMFD SP!,{r4-r12, LR}
 178   MOV   R1, R0                ; Save Function call in R1
 179   MRC   p15, 1, R6, c0, c0, 1 ; Read CLIDR
 180   ANDS  R3, R6, #&7000000     ; Mask out all but Level of Coherency (LoC)
 181   MOV   R3, R3, LSR #23       ; Cache level value (naturally aligned)
 182   BEQ   Finished
 183   MOV   R10, #0
 184
 185 Loop1
 186   ADD   R2, R10, R10, LSR #1  ; Work out 3xcachelevel
 187   MOV   R12, R6, LSR R2       ; bottom 3 bits are the Cache type for this level
 188   AND   R12, R12, #7          ; get those 3 bits alone
 189   CMP   R12, #2
 190   BLT   Skip                    ; no cache or only instruction cache at this level
 191   MCR   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 192   ISB                           ; ISB to sync the change to the CacheSizeID reg
 193   MRC   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)
 194   AND   R2, R12, #&7            ; extract the line length field
 195   ADD   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)
 196   LDR   R4, =0x3FF
 197   ANDS  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)
 198   CLZ   R5, R4                  ; R5 is the bit position of the way size increment
 199   LDR   R7, =0x00007FFF
 200   ANDS  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)
 201
 202 Loop2
 203   MOV   R9, R4                  ; R9 working copy of the max way size (right aligned)
 204
 205 Loop3
 206   ORR   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11
 207   ORR   R0, R0, R7, LSL R2      ; factor in the index number
 208
 209   BLX   R1
 210
 211   SUBS  R9, R9, #1              ; decrement the way number
 212   BGE   Loop3
 213   SUBS  R7, R7, #1              ; decrement the index
 214   BGE   Loop2
 215 Skip
 216   ADD   R10, R10, #2            ; increment the cache number
 217   CMP   R3, R10
 218   BGT   Loop1
 219
 220 Finished
 221   LDMFD SP!, {r4-r12, lr}
 222   BX    LR
 223
 224
 225 ArmDataMemoryBarrier
 226   DMB
 227   BX      LR
 228
 229 ArmDataSyncronizationBarrier
 230   DSB
 231   BX      LR
 232
 233 ArmInstructionSynchronizationBarrier
 234   ISB
 235   BX      LR
 236
 237     END