ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 //
   5 // This program and the accompanying materials
   6 // are licensed and made available under the terms and conditions of the BSD License
   7 // which accompanies this distribution.  The full text of the license may be found at
   8 // http://opensource.org/licenses/bsd-license.php
   9 //
  10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 //
  13 //------------------------------------------------------------------------------
  14
  15     EXPORT  ArmInvalidateInstructionCache
  16     EXPORT  ArmInvalidateDataCacheEntryByMVA
  17     EXPORT  ArmCleanDataCacheEntryByMVA
  18     EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
  19     EXPORT  ArmInvalidateDataCacheEntryBySetWay
  20     EXPORT  ArmCleanDataCacheEntryBySetWay
  21     EXPORT  ArmCleanInvalidateDataCacheEntryBySetWay
  22     EXPORT  ArmDrainWriteBuffer
  23     EXPORT  ArmEnableMmu
  24     EXPORT  ArmDisableMmu
  25     EXPORT  ArmDisableCachesAndMmu
  26     EXPORT  ArmMmuEnabled
  27     EXPORT  ArmEnableDataCache
  28     EXPORT  ArmDisableDataCache
  29     EXPORT  ArmEnableInstructionCache
  30     EXPORT  ArmDisableInstructionCache
  31     EXPORT  ArmEnableSWPInstruction
  32     EXPORT  ArmEnableBranchPrediction
  33     EXPORT  ArmDisableBranchPrediction
  34     EXPORT  ArmSetLowVectors
  35     EXPORT  ArmSetHighVectors
  36     EXPORT  ArmV7AllDataCachesOperation
  37     EXPORT  ArmDataMemoryBarrier
  38     EXPORT  ArmDataSyncronizationBarrier
  39     EXPORT  ArmInstructionSynchronizationBarrier
  40     EXPORT  ArmWriteNsacr
  41     EXPORT  ArmWriteScr
  42     EXPORT  ArmWriteVMBar
  43     EXPORT  ArmWriteVBar
  44     EXPORT  ArmReadVBar
  45     EXPORT  ArmWriteCPACR
  46     EXPORT  ArmEnableVFP
  47     EXPORT  ArmCallWFI
  48     EXPORT  ArmWriteAuxCr
  49     EXPORT  ArmReadAuxCr
  50     EXPORT  ArmReadCbar
  51     EXPORT  ArmInvalidateInstructionAndDataTlb
  52     EXPORT  ArmReadMpidr
  53
  54     AREA    ArmCacheLib, CODE, READONLY
  55     PRESERVE8
  56
  57 DC_ON           EQU     ( 0x1:SHL:2 )
  58 IC_ON           EQU     ( 0x1:SHL:12 )
  59 CTRL_M_BIT      EQU     (1 << 0)
  60 CTRL_C_BIT      EQU     (1 << 2)
  61 CTRL_B_BIT      EQU     (1 << 7)
  62 CTRL_I_BIT      EQU     (1 << 12)
  63
  64
  65 ArmInvalidateDataCacheEntryByMVA
  66   mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line
  67   dsb
  68   isb
  69   bx      lr
  70
  71
  72 ArmCleanDataCacheEntryByMVA
  73   mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line
  74   dsb
  75   isb
  76   bx      lr
  77
  78
  79 ArmCleanInvalidateDataCacheEntryByMVA
  80   mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  81   dsb
  82   isb
  83   bx      lr
  84
  85
  86 ArmInvalidateDataCacheEntryBySetWay
  87   mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line
  88   dsb
  89   isb
  90   bx      lr
  91
  92
  93 ArmCleanInvalidateDataCacheEntryBySetWay
  94   mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line
  95   dsb
  96   isb
  97   bx      lr
  98
  99
 100 ArmCleanDataCacheEntryBySetWay
 101   mcr     p15, 0, r0, c7, c10, 2       ; Clean this line
 102   dsb
 103   isb
 104   bx      lr
 105
 106
 107 ArmInvalidateInstructionCache
 108   mcr     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
 109   isb
 110   bx      LR
 111
 112 ArmEnableMmu
 113   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 114   orr     R0,R0,#1              ; Set SCTLR.M bit : Enable MMU
 115   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 116   dsb
 117   isb
 118   bx      LR
 119
 120 ArmMmuEnabled
 121   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 122   and     R0,R0,#1
 123   bx      LR
 124
 125 ArmDisableMmu
 126   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 127   bic     R0,R0,#1              ; Clear SCTLR.M bit : Disable MMU
 128   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 129
 130   mcr     p15,0,R0,c8,c7,0      ; TLBIALL : Invalidate unified TLB
 131   mcr     p15,0,R0,c7,c5,6      ; BPIALL  : Invalidate entire branch predictor array
 132   dsb
 133   isb
 134   bx      LR
 135
 136 ArmDisableCachesAndMmu
 137   mrc   p15, 0, r0, c1, c0, 0           ; Get control register
 138   bic   r0, r0, #CTRL_M_BIT             ; Disable MMU
 139   bic   r0, r0, #CTRL_C_BIT             ; Disable D Cache
 140   bic   r0, r0, #CTRL_I_BIT             ; Disable I Cache
 141   mcr   p15, 0, r0, c1, c0, 0           ; Write control register
 142   dsb
 143   isb
 144   bx      LR
 145
 146 ArmEnableDataCache
 147   ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
 148   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 149   orr     R0,R0,R1              ; Set SCTLR.C bit : Data and unified caches enabled
 150   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 151   dsb
 152   isb
 153   bx      LR
 154
 155 ArmDisableDataCache
 156   ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
 157   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 158   bic     R0,R0,R1              ; Clear SCTLR.C bit : Data and unified caches disabled
 159   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 160   isb
 161   bx      LR
 162
 163 ArmEnableInstructionCache
 164   ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
 165   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 166   orr     R0,R0,R1              ; Set SCTLR.I bit : Instruction caches enabled
 167   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 168   dsb
 169   isb
 170   bx      LR
 171
 172 ArmDisableInstructionCache
 173   ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
 174   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 175   BIC     R0,R0,R1              ; Clear SCTLR.I bit : Instruction caches disabled
 176   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 177   isb
 178   bx      LR
 179
 180 ArmEnableSWPInstruction
 181   mrc     p15, 0, r0, c1, c0, 0
 182   orr     r0, r0, #0x00000400
 183   mcr     p15, 0, r0, c1, c0, 0
 184   isb
 185   bx      LR
 186
 187 ArmEnableBranchPrediction
 188   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 189   orr     r0, r0, #0x00000800   ;
 190   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 191   isb
 192   bx      LR
 193
 194 ArmDisableBranchPrediction
 195   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 196   bic     r0, r0, #0x00000800   ;
 197   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 198   isb
 199   bx      LR
 200
 201 ArmSetLowVectors
 202   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 203   bic     r0, r0, #0x00002000   ; clear V bit
 204   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 205   isb
 206   bx      LR
 207
 208 ArmSetHighVectors
 209   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 210   orr     r0, r0, #0x00002000   ; clear V bit
 211   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 212   isb
 213   bx      LR
 214
 215 ArmV7AllDataCachesOperation
 216   stmfd SP!,{r4-r12, LR}
 217   mov   R1, R0                ; Save Function call in R1
 218   mrc   p15, 1, R6, c0, c0, 1 ; Read CLIDR
 219   ands  R3, R6, #&7000000     ; Mask out all but Level of Coherency (LoC)
 220   mov   R3, R3, LSR #23       ; Cache level value (naturally aligned)
 221   beq   Finished
 222   mov   R10, #0
 223
 224 Loop1
 225   add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel
 226   mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level
 227   and   R12, R12, #7            ; get those 3 bits alone
 228   cmp   R12, #2
 229   blt   Skip                    ; no cache or only instruction cache at this level
 230   mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 231   isb                           ; isb to sync the change to the CacheSizeID reg
 232   mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)
 233   and   R2, R12, #&7            ; extract the line length field
 234   add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)
 235   ldr   R4, =0x3FF
 236   ands  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)
 237   clz   R5, R4                  ; R5 is the bit position of the way size increment
 238   ldr   R7, =0x00007FFF
 239   ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)
 240
 241 Loop2
 242   mov   R9, R4                  ; R9 working copy of the max way size (right aligned)
 243
 244 Loop3
 245   orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11
 246   orr   R0, R0, R7, LSL R2      ; factor in the index number
 247
 248   blx   R1
 249
 250   subs  R9, R9, #1              ; decrement the way number
 251   bge   Loop3
 252   subs  R7, R7, #1              ; decrement the index
 253   bge   Loop2
 254 Skip
 255   add   R10, R10, #2            ; increment the cache number
 256   cmp   R3, R10
 257   bgt   Loop1
 258
 259 Finished
 260   dsb
 261   ldmfd SP!, {r4-r12, lr}
 262   bx    LR
 263
 264
 265 ArmDataMemoryBarrier
 266   dmb
 267   bx      LR
 268
 269 ArmDataSyncronizationBarrier
 270 ArmDrainWriteBuffer
 271   dsb
 272   bx      LR
 273
 274 ArmInstructionSynchronizationBarrier
 275   isb
 276   bx      LR
 277
 278 ArmWriteNsacr
 279   mcr     p15, 0, r0, c1, c1, 2
 280   bx      lr
 281
 282 ArmWriteScr
 283   mcr     p15, 0, r0, c1, c1, 0
 284   bx      lr
 285
 286 ArmWriteAuxCr
 287   mcr     p15, 0, r0, c1, c0, 1
 288   bx      lr
 289
 290 ArmReadAuxCr
 291   mrc     p15, 0, r0, c1, c0, 1
 292   bx      lr
 293
 294 ArmWriteVMBar
 295   mcr     p15, 0, r0, c12, c0, 1
 296   bx      lr
 297
 298 ArmWriteVBar
 299   // Set the Address of the Vector Table in the VBAR register
 300   mcr     p15, 0, r0, c12, c0, 0
 301   // Ensure the SCTLR.V bit is clear
 302   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 303   bic     r0, r0, #0x00002000   ; clear V bit
 304   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 305   isb
 306   bx      lr
 307
 308 ArmReadVBar
 309   mrc     p15, 0, r0, c12, c0, 0
 310   bx      lr
 311
 312 ArmWriteCPACR
 313   mcr     p15, 0, r0, c1, c0, 2
 314   bx      lr
 315
 316 ArmEnableVFP
 317   // Read CPACR (Coprocessor Access Control Register)
 318   mrc     p15, 0, r0, c1, c0, 2
 319   // Enable VPF access (Full Access to CP10, CP11) (V* instructions)
 320   orr     r0, r0, #0x00f00000
 321   // Write back CPACR (Coprocessor Access Control Register)
 322   mcr     p15, 0, r0, c1, c0, 2
 323   // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
 324   mov     r0, #0x40000000
 325   mcr     p10,#0x7,r0,c8,c0,#0
 326   bx      lr
 327
 328 ArmCallWFI
 329   wfi
 330   bx      lr
 331
 332 //Note: Return 0 in Uniprocessor implementation
 333 ArmReadCbar
 334   mrc     p15, 4, r0, c15, c0, 0  //Read Configuration Base Address Register
 335   bx      lr
 336
 337 ArmInvalidateInstructionAndDataTlb
 338   mcr     p15, 0, r0, c8, c7, 0      ; Invalidate Inst TLB and Data TLB
 339   dsb
 340   bx lr
 341
 342 ArmReadMpidr
 343   mrc     p15, 0, r0, c0, c0, 5    ; read MPIDR
 344   bx      lr
 345
 346   END
 347