ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 //
   6 // This program and the accompanying materials
   7 // are licensed and made available under the terms and conditions of the BSD License
   8 // which accompanies this distribution.  The full text of the license may be found at
   9 // http://opensource.org/licenses/bsd-license.php
  10 //
  11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 //
  14 //------------------------------------------------------------------------------
  15
  16     EXPORT  ArmInvalidateInstructionCache
  17     EXPORT  ArmInvalidateDataCacheEntryByMVA
  18     EXPORT  ArmCleanDataCacheEntryByMVA
  19     EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
  20     EXPORT  ArmInvalidateDataCacheEntryBySetWay
  21     EXPORT  ArmCleanDataCacheEntryBySetWay
  22     EXPORT  ArmCleanInvalidateDataCacheEntryBySetWay
  23     EXPORT  ArmDrainWriteBuffer
  24     EXPORT  ArmEnableMmu
  25     EXPORT  ArmDisableMmu
  26     EXPORT  ArmDisableCachesAndMmu
  27     EXPORT  ArmMmuEnabled
  28     EXPORT  ArmEnableDataCache
  29     EXPORT  ArmDisableDataCache
  30     EXPORT  ArmEnableInstructionCache
  31     EXPORT  ArmDisableInstructionCache
  32     EXPORT  ArmEnableSWPInstruction
  33     EXPORT  ArmEnableBranchPrediction
  34     EXPORT  ArmDisableBranchPrediction
  35     EXPORT  ArmSetLowVectors
  36     EXPORT  ArmSetHighVectors
  37     EXPORT  ArmV7AllDataCachesOperation
  38     EXPORT  ArmV7PerformPoUDataCacheOperation
  39     EXPORT  ArmDataMemoryBarrier
  40     EXPORT  ArmDataSyncronizationBarrier
  41     EXPORT  ArmInstructionSynchronizationBarrier
  42     EXPORT  ArmReadVBar
  43     EXPORT  ArmWriteVBar
  44     EXPORT  ArmEnableVFP
  45     EXPORT  ArmCallWFI
  46     EXPORT  ArmReadCbar
  47     EXPORT  ArmInvalidateInstructionAndDataTlb
  48     EXPORT  ArmReadMpidr
  49     EXPORT  ArmReadMidr
  50     EXPORT  ArmReadTpidrurw
  51     EXPORT  ArmWriteTpidrurw
  52     EXPORT  ArmIsArchTimerImplemented
  53     EXPORT  ArmReadIdPfr1
  54
  55     AREA    ArmV7Support, CODE, READONLY
  56     PRESERVE8
  57
  58 DC_ON           EQU     ( 0x1:SHL:2 )
  59 IC_ON           EQU     ( 0x1:SHL:12 )
  60 CTRL_M_BIT      EQU     (1 << 0)
  61 CTRL_C_BIT      EQU     (1 << 2)
  62 CTRL_B_BIT      EQU     (1 << 7)
  63 CTRL_I_BIT      EQU     (1 << 12)
  64
  65
  66 ArmInvalidateDataCacheEntryByMVA
  67   mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line
  68   dsb
  69   isb
  70   bx      lr
  71
  72 ArmCleanDataCacheEntryByMVA
  73   mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line
  74   dsb
  75   isb
  76   bx      lr
  77
  78
  79 ArmCleanInvalidateDataCacheEntryByMVA
  80   mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  81   dsb
  82   isb
  83   bx      lr
  84
  85
  86 ArmInvalidateDataCacheEntryBySetWay
  87   mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line
  88   dsb
  89   isb
  90   bx      lr
  91
  92
  93 ArmCleanInvalidateDataCacheEntryBySetWay
  94   mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line
  95   dsb
  96   isb
  97   bx      lr
  98
  99
 100 ArmCleanDataCacheEntryBySetWay
 101   mcr     p15, 0, r0, c7, c10, 2       ; Clean this line
 102   dsb
 103   isb
 104   bx      lr
 105
 106
 107 ArmInvalidateInstructionCache
 108   mcr     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
 109   isb
 110   bx      LR
 111
 112 ArmEnableMmu
 113   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 114   orr     R0,R0,#1              ; Set SCTLR.M bit : Enable MMU
 115   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 116   dsb
 117   isb
 118   bx      LR
 119
 120 ArmDisableMmu
 121   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 122   bic     R0,R0,#1              ; Clear SCTLR.M bit : Disable MMU
 123   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 124
 125   mcr     p15,0,R0,c8,c7,0      ; TLBIALL : Invalidate unified TLB
 126   mcr     p15,0,R0,c7,c5,6      ; BPIALL  : Invalidate entire branch predictor array
 127   dsb
 128   isb
 129   bx      LR
 130
 131 ArmDisableCachesAndMmu
 132   mrc   p15, 0, r0, c1, c0, 0           ; Get control register
 133   bic   r0, r0, #CTRL_M_BIT             ; Disable MMU
 134   bic   r0, r0, #CTRL_C_BIT             ; Disable D Cache
 135   bic   r0, r0, #CTRL_I_BIT             ; Disable I Cache
 136   mcr   p15, 0, r0, c1, c0, 0           ; Write control register
 137   dsb
 138   isb
 139   bx      LR
 140
 141 ArmMmuEnabled
 142   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 143   and     R0,R0,#1
 144   bx      LR
 145
 146 ArmEnableDataCache
 147   ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
 148   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 149   orr     R0,R0,R1              ; Set SCTLR.C bit : Data and unified caches enabled
 150   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 151   dsb
 152   isb
 153   bx      LR
 154
 155 ArmDisableDataCache
 156   ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
 157   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 158   bic     R0,R0,R1              ; Clear SCTLR.C bit : Data and unified caches disabled
 159   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 160   dsb
 161   isb
 162   bx      LR
 163
 164 ArmEnableInstructionCache
 165   ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
 166   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 167   orr     R0,R0,R1              ; Set SCTLR.I bit : Instruction caches enabled
 168   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 169   dsb
 170   isb
 171   bx      LR
 172
 173 ArmDisableInstructionCache
 174   ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
 175   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 176   BIC     R0,R0,R1              ; Clear SCTLR.I bit : Instruction caches disabled
 177   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 178   isb
 179   bx      LR
 180
 181 ArmEnableSWPInstruction
 182   mrc     p15, 0, r0, c1, c0, 0
 183   orr     r0, r0, #0x00000400
 184   mcr     p15, 0, r0, c1, c0, 0
 185   isb
 186   bx      LR
 187
 188 ArmEnableBranchPrediction
 189   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 190   orr     r0, r0, #0x00000800   ;
 191   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 192   dsb
 193   isb
 194   bx      LR
 195
 196 ArmDisableBranchPrediction
 197   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 198   bic     r0, r0, #0x00000800   ;
 199   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 200   dsb
 201   isb
 202   bx      LR
 203
 204 ArmSetLowVectors
 205   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 206   bic     r0, r0, #0x00002000   ; clear V bit
 207   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 208   isb
 209   bx      LR
 210
 211 ArmSetHighVectors
 212   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 213   orr     r0, r0, #0x00002000   ; Set V bit
 214   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 215   isb
 216   bx      LR
 217
 218 ArmV7AllDataCachesOperation
 219   stmfd SP!,{r4-r12, LR}
 220   mov   R1, R0                ; Save Function call in R1
 221   mrc   p15, 1, R6, c0, c0, 1 ; Read CLIDR
 222   ands  R3, R6, #&7000000     ; Mask out all but Level of Coherency (LoC)
 223   mov   R3, R3, LSR #23       ; Cache level value (naturally aligned)
 224   beq   Finished
 225   mov   R10, #0
 226
 227 Loop1
 228   add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel
 229   mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level
 230   and   R12, R12, #7            ; get those 3 bits alone
 231   cmp   R12, #2
 232   blt   Skip                    ; no cache or only instruction cache at this level
 233   mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 234   isb                           ; isb to sync the change to the CacheSizeID reg
 235   mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)
 236   and   R2, R12, #&7            ; extract the line length field
 237   add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)
 238   ldr   R4, =0x3FF
 239   ands  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)
 240   clz   R5, R4                  ; R5 is the bit position of the way size increment
 241   ldr   R7, =0x00007FFF
 242   ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)
 243
 244 Loop2
 245   mov   R9, R4                  ; R9 working copy of the max way size (right aligned)
 246
 247 Loop3
 248   orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11
 249   orr   R0, R0, R7, LSL R2      ; factor in the index number
 250
 251   blx   R1
 252
 253   subs  R9, R9, #1              ; decrement the way number
 254   bge   Loop3
 255   subs  R7, R7, #1              ; decrement the index
 256   bge   Loop2
 257 Skip
 258   add   R10, R10, #2            ; increment the cache number
 259   cmp   R3, R10
 260   bgt   Loop1
 261
 262 Finished
 263   dsb
 264   ldmfd SP!, {r4-r12, lr}
 265   bx    LR
 266
 267 ArmV7PerformPoUDataCacheOperation
 268   stmfd SP!,{r4-r12, LR}
 269   mov   R1, R0                ; Save Function call in R1
 270   mrc   p15, 1, R6, c0, c0, 1 ; Read CLIDR
 271   ands  R3, R6, #&38000000    ; Mask out all but Level of Unification (LoU)
 272   mov   R3, R3, LSR #26       ; Cache level value (naturally aligned)
 273   beq   Finished2
 274   mov   R10, #0
 275
 276 Loop4
 277   add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel
 278   mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level
 279   and   R12, R12, #7            ; get those 3 bits alone
 280   cmp   R12, #2
 281   blt   Skip2                   ; no cache or only instruction cache at this level
 282   mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 283   isb                           ; isb to sync the change to the CacheSizeID reg
 284   mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)
 285   and   R2, R12, #&7            ; extract the line length field
 286   add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)
 287   ldr   R4, =0x3FF
 288   ands  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)
 289   clz   R5, R4                  ; R5 is the bit position of the way size increment
 290   ldr   R7, =0x00007FFF
 291   ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)
 292
 293 Loop5
 294   mov   R9, R4                  ; R9 working copy of the max way size (right aligned)
 295
 296 Loop6
 297   orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11
 298   orr   R0, R0, R7, LSL R2      ; factor in the index number
 299
 300   blx   R1
 301
 302   subs  R9, R9, #1              ; decrement the way number
 303   bge   Loop6
 304   subs  R7, R7, #1              ; decrement the index
 305   bge   Loop5
 306 Skip2
 307   add   R10, R10, #2            ; increment the cache number
 308   cmp   R3, R10
 309   bgt   Loop4
 310
 311 Finished2
 312   dsb
 313   ldmfd SP!, {r4-r12, lr}
 314   bx    LR
 315
 316 ArmDataMemoryBarrier
 317   dmb
 318   bx      LR
 319
 320 ArmDataSyncronizationBarrier
 321 ArmDrainWriteBuffer
 322   dsb
 323   bx      LR
 324
 325 ArmInstructionSynchronizationBarrier
 326   isb
 327   bx      LR
 328
 329 ArmReadVBar
 330   // Set the Address of the Vector Table in the VBAR register
 331   mrc     p15, 0, r0, c12, c0, 0
 332   bx      lr
 333
 334 ArmWriteVBar
 335   // Set the Address of the Vector Table in the VBAR register
 336   mcr     p15, 0, r0, c12, c0, 0
 337   // Ensure the SCTLR.V bit is clear
 338   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 339   bic     r0, r0, #0x00002000   ; clear V bit
 340   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 341   isb
 342   bx      lr
 343
 344 ArmEnableVFP
 345   // Read CPACR (Coprocessor Access Control Register)
 346   mrc     p15, 0, r0, c1, c0, 2
 347   // Enable VPF access (Full Access to CP10, CP11) (V* instructions)
 348   orr     r0, r0, #0x00f00000
 349   // Write back CPACR (Coprocessor Access Control Register)
 350   mcr     p15, 0, r0, c1, c0, 2
 351   isb
 352   // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
 353   mov     r0, #0x40000000
 354   mcr     p10,#0x7,r0,c8,c0,#0
 355   bx      lr
 356
 357 ArmCallWFI
 358   wfi
 359   bx      lr
 360
 361 //Note: Return 0 in Uniprocessor implementation
 362 ArmReadCbar
 363   mrc     p15, 4, r0, c15, c0, 0  //Read Configuration Base Address Register
 364   bx      lr
 365
 366 ArmInvalidateInstructionAndDataTlb
 367   mcr     p15, 0, r0, c8, c7, 0      ; Invalidate Inst TLB and Data TLB
 368   dsb
 369   bx lr
 370
 371 ArmReadMpidr
 372   mrc     p15, 0, r0, c0, c0, 5     ; read MPIDR
 373   bx      lr
 374
 375 ArmReadMidr
 376   mrc     p15, 0, r0, c0, c0, 0      ; Read Main ID Register
 377   bx      lr
 378
 379 ArmReadTpidrurw
 380   mrc     p15, 0, r0, c13, c0, 2    ; read TPIDRURW
 381   bx      lr
 382
 383 ArmWriteTpidrurw
 384   mcr     p15, 0, r0, c13, c0, 2   ; write TPIDRURW
 385   bx      lr
 386
 387 ArmIsArchTimerImplemented
 388   mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1
 389   and    r0, r0, #0x000F0000
 390   bx     lr
 391
 392 ArmReadIdPfr1
 393   mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1 Register
 394   bx     lr
 395
 396  END