ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 //
   6 // This program and the accompanying materials
   7 // are licensed and made available under the terms and conditions of the BSD License
   8 // which accompanies this distribution.  The full text of the license may be found at
   9 // http://opensource.org/licenses/bsd-license.php
  10 //
  11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 //
  14 //------------------------------------------------------------------------------
  15
  16
  17     INCLUDE AsmMacroExport.inc
  18     PRESERVE8
  19
  20 DC_ON           EQU     ( 0x1:SHL:2 )
  21 IC_ON           EQU     ( 0x1:SHL:12 )
  22 CTRL_M_BIT      EQU     (1 << 0)
  23 CTRL_C_BIT      EQU     (1 << 2)
  24 CTRL_B_BIT      EQU     (1 << 7)
  25 CTRL_I_BIT      EQU     (1 << 12)
  26
  27
  28  RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryByMVA
  29   mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line
  30   bx      lr
  31
  32  RVCT_ASM_EXPORT ArmCleanDataCacheEntryByMVA
  33   mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line
  34   bx      lr
  35
  36
  37  RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA
  38   mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  39   bx      lr
  40
  41
  42  RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryBySetWay
  43   mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line
  44   bx      lr
  45
  46
  47  RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
  48   mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line
  49   bx      lr
  50
  51
  52  RVCT_ASM_EXPORT ArmCleanDataCacheEntryBySetWay
  53   mcr     p15, 0, r0, c7, c10, 2       ; Clean this line
  54   bx      lr
  55
  56
  57  RVCT_ASM_EXPORT ArmInvalidateInstructionCache
  58   mcr     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
  59   isb
  60   bx      LR
  61
  62  RVCT_ASM_EXPORT ArmEnableMmu
  63   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
  64   orr     R0,R0,#1              ; Set SCTLR.M bit : Enable MMU
  65   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
  66   dsb
  67   isb
  68   bx      LR
  69
  70  RVCT_ASM_EXPORT ArmDisableMmu
  71   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
  72   bic     R0,R0,#1              ; Clear SCTLR.M bit : Disable MMU
  73   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
  74
  75   mcr     p15,0,R0,c8,c7,0      ; TLBIALL : Invalidate unified TLB
  76   mcr     p15,0,R0,c7,c5,6      ; BPIALL  : Invalidate entire branch predictor array
  77   dsb
  78   isb
  79   bx      LR
  80
  81  RVCT_ASM_EXPORT ArmDisableCachesAndMmu
  82   mrc   p15, 0, r0, c1, c0, 0           ; Get control register
  83   bic   r0, r0, #CTRL_M_BIT             ; Disable MMU
  84   bic   r0, r0, #CTRL_C_BIT             ; Disable D Cache
  85   bic   r0, r0, #CTRL_I_BIT             ; Disable I Cache
  86   mcr   p15, 0, r0, c1, c0, 0           ; Write control register
  87   dsb
  88   isb
  89   bx      LR
  90
  91  RVCT_ASM_EXPORT ArmMmuEnabled
  92   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
  93   and     R0,R0,#1
  94   bx      LR
  95
  96  RVCT_ASM_EXPORT ArmEnableDataCache
  97   ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
  98   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
  99   orr     R0,R0,R1              ; Set SCTLR.C bit : Data and unified caches enabled
 100   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 101   dsb
 102   isb
 103   bx      LR
 104
 105  RVCT_ASM_EXPORT ArmDisableDataCache
 106   ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
 107   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 108   bic     R0,R0,R1              ; Clear SCTLR.C bit : Data and unified caches disabled
 109   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 110   dsb
 111   isb
 112   bx      LR
 113
 114  RVCT_ASM_EXPORT ArmEnableInstructionCache
 115   ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
 116   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 117   orr     R0,R0,R1              ; Set SCTLR.I bit : Instruction caches enabled
 118   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 119   dsb
 120   isb
 121   bx      LR
 122
 123  RVCT_ASM_EXPORT ArmDisableInstructionCache
 124   ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
 125   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 126   BIC     R0,R0,R1              ; Clear SCTLR.I bit : Instruction caches disabled
 127   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 128   isb
 129   bx      LR
 130
 131  RVCT_ASM_EXPORT ArmEnableSWPInstruction
 132   mrc     p15, 0, r0, c1, c0, 0
 133   orr     r0, r0, #0x00000400
 134   mcr     p15, 0, r0, c1, c0, 0
 135   isb
 136   bx      LR
 137
 138  RVCT_ASM_EXPORT ArmEnableBranchPrediction
 139   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 140   orr     r0, r0, #0x00000800   ;
 141   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 142   dsb
 143   isb
 144   bx      LR
 145
 146  RVCT_ASM_EXPORT ArmDisableBranchPrediction
 147   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 148   bic     r0, r0, #0x00000800   ;
 149   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 150   dsb
 151   isb
 152   bx      LR
 153
 154  RVCT_ASM_EXPORT ArmSetLowVectors
 155   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 156   bic     r0, r0, #0x00002000   ; clear V bit
 157   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 158   isb
 159   bx      LR
 160
 161  RVCT_ASM_EXPORT ArmSetHighVectors
 162   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 163   orr     r0, r0, #0x00002000   ; Set V bit
 164   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 165   isb
 166   bx      LR
 167
 168  RVCT_ASM_EXPORT ArmV7AllDataCachesOperation
 169   stmfd SP!,{r4-r12, LR}
 170   mov   R1, R0                ; Save Function call in R1
 171   mrc   p15, 1, R6, c0, c0, 1 ; Read CLIDR
 172   ands  R3, R6, #&7000000     ; Mask out all but Level of Coherency (LoC)
 173   mov   R3, R3, LSR #23       ; Cache level value (naturally aligned)
 174   beq   Finished
 175   mov   R10, #0
 176
 177 Loop1
 178   add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel
 179   mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level
 180   and   R12, R12, #7            ; get those 3 bits alone
 181   cmp   R12, #2
 182   blt   Skip                    ; no cache or only instruction cache at this level
 183   mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 184   isb                           ; isb to sync the change to the CacheSizeID reg
 185   mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)
 186   and   R2, R12, #&7            ; extract the line length field
 187   add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)
 188   ldr   R4, =0x3FF
 189   ands  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)
 190   clz   R5, R4                  ; R5 is the bit position of the way size increment
 191   ldr   R7, =0x00007FFF
 192   ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)
 193
 194 Loop2
 195   mov   R9, R4                  ; R9 working copy of the max way size (right aligned)
 196
 197 Loop3
 198   orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11
 199   orr   R0, R0, R7, LSL R2      ; factor in the index number
 200
 201   blx   R1
 202
 203   subs  R9, R9, #1              ; decrement the way number
 204   bge   Loop3
 205   subs  R7, R7, #1              ; decrement the index
 206   bge   Loop2
 207 Skip
 208   add   R10, R10, #2            ; increment the cache number
 209   cmp   R3, R10
 210   bgt   Loop1
 211
 212 Finished
 213   dsb
 214   ldmfd SP!, {r4-r12, lr}
 215   bx    LR
 216
 217  RVCT_ASM_EXPORT ArmDataMemoryBarrier
 218   dmb
 219   bx      LR
 220
 221  RVCT_ASM_EXPORT ArmDataSynchronizationBarrier
 222   dsb
 223   bx      LR
 224
 225  RVCT_ASM_EXPORT ArmInstructionSynchronizationBarrier
 226   isb
 227   bx      LR
 228
 229  RVCT_ASM_EXPORT ArmReadVBar
 230   // Set the Address of the Vector Table in the VBAR register
 231   mrc     p15, 0, r0, c12, c0, 0
 232   bx      lr
 233
 234  RVCT_ASM_EXPORT ArmWriteVBar
 235   // Set the Address of the Vector Table in the VBAR register
 236   mcr     p15, 0, r0, c12, c0, 0
 237   // Ensure the SCTLR.V bit is clear
 238   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 239   bic     r0, r0, #0x00002000   ; clear V bit
 240   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 241   isb
 242   bx      lr
 243
 244  RVCT_ASM_EXPORT ArmEnableVFP
 245   // Read CPACR (Coprocessor Access Control Register)
 246   mrc     p15, 0, r0, c1, c0, 2
 247   // Enable VPF access (Full Access to CP10, CP11) (V* instructions)
 248   orr     r0, r0, #0x00f00000
 249   // Write back CPACR (Coprocessor Access Control Register)
 250   mcr     p15, 0, r0, c1, c0, 2
 251   isb
 252   // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
 253   mov     r0, #0x40000000
 254   mcr     p10,#0x7,r0,c8,c0,#0
 255   bx      lr
 256
 257  RVCT_ASM_EXPORT ArmCallWFI
 258   wfi
 259   bx      lr
 260
 261 //Note: Return 0 in Uniprocessor implementation
 262  RVCT_ASM_EXPORT ArmReadCbar
 263   mrc     p15, 4, r0, c15, c0, 0  //Read Configuration Base Address Register
 264   bx      lr
 265
 266  RVCT_ASM_EXPORT ArmReadMpidr
 267   mrc     p15, 0, r0, c0, c0, 5     ; read MPIDR
 268   bx      lr
 269
 270  RVCT_ASM_EXPORT ArmReadTpidrurw
 271   mrc     p15, 0, r0, c13, c0, 2    ; read TPIDRURW
 272   bx      lr
 273
 274  RVCT_ASM_EXPORT ArmWriteTpidrurw
 275   mcr     p15, 0, r0, c13, c0, 2   ; write TPIDRURW
 276   bx      lr
 277
 278  RVCT_ASM_EXPORT ArmIsArchTimerImplemented
 279   mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1
 280   and    r0, r0, #0x000F0000
 281   bx     lr
 282
 283  RVCT_ASM_EXPORT ArmReadIdPfr1
 284   mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1 Register
 285   bx     lr
 286
 287  RVCT_ASM_EXPORT ArmReadIdMmfr0
 288   mrc    p15, 0, r0, c0, c1, 4     ; Read ID_MMFR0 Register
 289   bx     lr
 290
 291  END