ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 #include <AsmMacroIoLib.h>
  17
  18 .text
  19 .align 2
  20 GCC_ASM_EXPORT(ArmReadMidr)
  21 GCC_ASM_EXPORT(ArmCacheInfo)
  22 GCC_ASM_EXPORT(ArmGetInterruptState)
  23 GCC_ASM_EXPORT(ArmGetFiqState)
  24 GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
  25 GCC_ASM_EXPORT(ArmSetTTBR0)
  26 GCC_ASM_EXPORT(ArmSetDomainAccessControl)
  27 GCC_ASM_EXPORT(CPSRMaskInsert)
  28 GCC_ASM_EXPORT(CPSRRead)
  29 GCC_ASM_EXPORT(ArmReadCpacr)
  30 GCC_ASM_EXPORT(ArmWriteCpacr)
  31 GCC_ASM_EXPORT(ArmWriteAuxCr)
  32 GCC_ASM_EXPORT(ArmReadAuxCr)
  33 GCC_ASM_EXPORT(ArmInvalidateTlb)
  34 GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
  35 GCC_ASM_EXPORT(ArmReadScr)
  36 GCC_ASM_EXPORT(ArmWriteScr)
  37 GCC_ASM_EXPORT(ArmReadMVBar)
  38 GCC_ASM_EXPORT(ArmWriteMVBar)
  39 GCC_ASM_EXPORT(ArmReadHVBar)
  40 GCC_ASM_EXPORT(ArmWriteHVBar)
  41 GCC_ASM_EXPORT(ArmCallWFE)
  42 GCC_ASM_EXPORT(ArmCallSEV)
  43 GCC_ASM_EXPORT(ArmReadSctlr)
  44 GCC_ASM_EXPORT(ArmReadCpuActlr)
  45 GCC_ASM_EXPORT(ArmWriteCpuActlr)
  46
  47 #------------------------------------------------------------------------------
  48
  49 ASM_PFX(ArmReadMidr):
  50   mrc     p15,0,R0,c0,c0,0
  51   bx      LR
  52
  53 ASM_PFX(ArmCacheInfo):
  54   mrc     p15,0,R0,c0,c0,1
  55   bx      LR
  56
  57 ASM_PFX(ArmGetInterruptState):
  58   mrs     R0,CPSR
  59   tst     R0,#0x80      @Check if IRQ is enabled.
  60   moveq   R0,#1
  61   movne   R0,#0
  62   bx      LR
  63
  64 ASM_PFX(ArmGetFiqState):
  65   mrs     R0,CPSR
  66   tst     R0,#0x40      @Check if FIQ is enabled.
  67   moveq   R0,#1
  68   movne   R0,#0
  69   bx      LR
  70
  71 ASM_PFX(ArmSetDomainAccessControl):
  72   mcr     p15,0,r0,c3,c0,0
  73   bx      lr
  74
  75 ASM_PFX(CPSRMaskInsert):    @ on entry, r0 is the mask and r1 is the field to insert
  76   stmfd   sp!, {r4-r12, lr} @ save all the banked registers
  77   mov     r3, sp            @ copy the stack pointer into a non-banked register
  78   mrs     r2, cpsr          @ read the cpsr
  79   bic     r2, r2, r0        @ clear mask in the cpsr
  80   and     r1, r1, r0        @ clear bits outside the mask in the input
  81   orr     r2, r2, r1        @ set field
  82   msr     cpsr_cxsf, r2     @ write back cpsr (may have caused a mode switch)
  83   isb
  84   mov     sp, r3            @ restore stack pointer
  85   ldmfd   sp!, {r4-r12, lr} @ restore registers
  86   bx      lr                @ return (hopefully thumb-safe!)
  87
  88 ASM_PFX(CPSRRead):
  89   mrs     r0, cpsr
  90   bx      lr
  91
  92 ASM_PFX(ArmReadCpacr):
  93   mrc     p15, 0, r0, c1, c0, 2
  94   bx      lr
  95
  96 ASM_PFX(ArmWriteCpacr):
  97   mcr     p15, 0, r0, c1, c0, 2
  98   isb
  99   bx      lr
 100
 101 ASM_PFX(ArmWriteAuxCr):
 102   mcr     p15, 0, r0, c1, c0, 1
 103   bx      lr
 104
 105 ASM_PFX(ArmReadAuxCr):
 106   mrc     p15, 0, r0, c1, c0, 1
 107   bx      lr
 108
 109 ASM_PFX(ArmSetTTBR0):
 110   mcr     p15,0,r0,c2,c0,0
 111   isb
 112   bx      lr
 113
 114 ASM_PFX(ArmGetTTBR0BaseAddress):
 115   mrc     p15,0,r0,c2,c0,0
 116   LoadConstantToReg(0xFFFFC000, r1)
 117   and     r0, r0, r1
 118   isb
 119   bx      lr
 120
 121 //
 122 //VOID
 123 //ArmUpdateTranslationTableEntry (
 124 //  IN VOID  *TranslationTableEntry  // R0
 125 //  IN VOID  *MVA                    // R1
 126 //  );
 127 ASM_PFX(ArmUpdateTranslationTableEntry):
 128   mcr     p15,0,R0,c7,c14,1     @ DCCIMVAC Clean data cache by MVA
 129   dsb
 130   mcr     p15,0,R1,c8,c7,1      @ TLBIMVA TLB Invalidate MVA
 131   mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp
 132   dsb
 133   isb
 134   bx      lr
 135
 136 ASM_PFX(ArmInvalidateTlb):
 137   mov     r0,#0
 138   mcr     p15,0,r0,c8,c7,0
 139   mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp
 140   dsb
 141   isb
 142   bx      lr
 143
 144 ASM_PFX(ArmReadScr):
 145   mrc     p15, 0, r0, c1, c1, 0
 146   bx      lr
 147
 148 ASM_PFX(ArmWriteScr):
 149   mcr     p15, 0, r0, c1, c1, 0
 150   isb
 151   bx      lr
 152
 153 ASM_PFX(ArmReadHVBar):
 154   mrc     p15, 4, r0, c12, c0, 0
 155   bx      lr
 156
 157 ASM_PFX(ArmWriteHVBar):
 158   mcr     p15, 4, r0, c12, c0, 0
 159   bx      lr
 160
 161 ASM_PFX(ArmReadMVBar):
 162   mrc     p15, 0, r0, c12, c0, 1
 163   bx      lr
 164
 165 ASM_PFX(ArmWriteMVBar):
 166   mcr     p15, 0, r0, c12, c0, 1
 167   bx      lr
 168
 169 ASM_PFX(ArmCallWFE):
 170   wfe
 171   bx      lr
 172
 173 ASM_PFX(ArmCallSEV):
 174   sev
 175   bx      lr
 176
 177 ASM_PFX(ArmReadSctlr):
 178   mrc     p15, 0, r0, c1, c0, 0      @ Read SCTLR into R0 (Read control register configuration data)
 179   bx      lr
 180
 181 ASM_PFX(ArmReadCpuActlr):
 182   mrc     p15, 0, r0, c1, c0, 1
 183   bx      lr
 184
 185 ASM_PFX(ArmWriteCpuActlr):
 186   mcr     p15, 0, r0, c1, c0, 1
 187   dsb
 188   isb
 189   bx      lr
 190
 191 ASM_FUNCTION_REMOVE_IF_UNREFERENCED