ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011-2013, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 #include <AsmMacroIoLib.h>
  17
  18 #ifdef ARM_CPU_ARMv6
  19 // No memory barriers for ARMv6
  20 #define isb
  21 #define dsb
  22 #endif
  23
  24 .text
  25 .align 2
  26 GCC_ASM_EXPORT(Cp15IdCode)
  27 GCC_ASM_EXPORT(Cp15CacheInfo)
  28 GCC_ASM_EXPORT(ArmGetInterruptState)
  29 GCC_ASM_EXPORT(ArmGetFiqState)
  30 GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
  31 GCC_ASM_EXPORT(ArmSetTTBR0)
  32 GCC_ASM_EXPORT(ArmSetDomainAccessControl)
  33 GCC_ASM_EXPORT(CPSRMaskInsert)
  34 GCC_ASM_EXPORT(CPSRRead)
  35 GCC_ASM_EXPORT(ArmReadCpacr)
  36 GCC_ASM_EXPORT(ArmWriteCpacr)
  37 GCC_ASM_EXPORT(ArmWriteAuxCr)
  38 GCC_ASM_EXPORT(ArmReadAuxCr)
  39 GCC_ASM_EXPORT(ArmInvalidateTlb)
  40 GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
  41 GCC_ASM_EXPORT(ArmReadNsacr)
  42 GCC_ASM_EXPORT(ArmWriteNsacr)
  43 GCC_ASM_EXPORT(ArmReadScr)
  44 GCC_ASM_EXPORT(ArmWriteScr)
  45 GCC_ASM_EXPORT(ArmReadMVBar)
  46 GCC_ASM_EXPORT(ArmWriteMVBar)
  47 GCC_ASM_EXPORT(ArmReadHVBar)
  48 GCC_ASM_EXPORT(ArmWriteHVBar)
  49 GCC_ASM_EXPORT(ArmCallWFE)
  50 GCC_ASM_EXPORT(ArmCallSEV)
  51 GCC_ASM_EXPORT(ArmReadSctlr)
  52
  53 #------------------------------------------------------------------------------
  54
  55 ASM_PFX(Cp15IdCode):
  56   mrc     p15,0,R0,c0,c0,0
  57   bx      LR
  58
  59 ASM_PFX(Cp15CacheInfo):
  60   mrc     p15,0,R0,c0,c0,1
  61   bx      LR
  62
  63 ASM_PFX(ArmGetInterruptState):
  64   mrs     R0,CPSR
  65   tst     R0,#0x80      @Check if IRQ is enabled.
  66   moveq   R0,#1
  67   movne   R0,#0
  68   bx      LR
  69
  70 ASM_PFX(ArmGetFiqState):
  71   mrs     R0,CPSR
  72   tst     R0,#0x40      @Check if FIQ is enabled.
  73   moveq   R0,#1
  74   movne   R0,#0
  75   bx      LR
  76
  77 ASM_PFX(ArmSetDomainAccessControl):
  78   mcr     p15,0,r0,c3,c0,0
  79   bx      lr
  80
  81 ASM_PFX(CPSRMaskInsert):    @ on entry, r0 is the mask and r1 is the field to insert
  82   stmfd   sp!, {r4-r12, lr} @ save all the banked registers
  83   mov     r3, sp            @ copy the stack pointer into a non-banked register
  84   mrs     r2, cpsr          @ read the cpsr
  85   bic     r2, r2, r0        @ clear mask in the cpsr
  86   and     r1, r1, r0        @ clear bits outside the mask in the input
  87   orr     r2, r2, r1        @ set field
  88   msr     cpsr_cxsf, r2     @ write back cpsr (may have caused a mode switch)
  89   isb
  90   mov     sp, r3            @ restore stack pointer
  91   ldmfd   sp!, {r4-r12, lr} @ restore registers
  92   bx      lr                @ return (hopefully thumb-safe!)             @ return (hopefully thumb-safe!)
  93
  94 ASM_PFX(CPSRRead):
  95   mrs     r0, cpsr
  96   bx      lr
  97
  98 ASM_PFX(ArmReadCpacr):
  99   mrc     p15, 0, r0, c1, c0, 2
 100   bx      lr
 101
 102 ASM_PFX(ArmWriteCpacr):
 103   mcr     p15, 0, r0, c1, c0, 2
 104   isb
 105   bx      lr
 106
 107 ASM_PFX(ArmWriteAuxCr):
 108   mcr     p15, 0, r0, c1, c0, 1
 109   bx      lr
 110
 111 ASM_PFX(ArmReadAuxCr):
 112   mrc     p15, 0, r0, c1, c0, 1
 113   bx      lr
 114
 115 ASM_PFX(ArmSetTTBR0):
 116   mcr     p15,0,r0,c2,c0,0
 117   isb
 118   bx      lr
 119
 120 ASM_PFX(ArmGetTTBR0BaseAddress):
 121   mrc     p15,0,r0,c2,c0,0
 122   LoadConstantToReg(0xFFFFC000, r1)
 123   and     r0, r0, r1
 124   isb
 125   bx      lr
 126
 127 //
 128 //VOID
 129 //ArmUpdateTranslationTableEntry (
 130 //  IN VOID  *TranslationTableEntry  // R0
 131 //  IN VOID  *MVA                    // R1
 132 //  );
 133 ASM_PFX(ArmUpdateTranslationTableEntry):
 134   mcr     p15,0,R0,c7,c14,1     @ DCCIMVAC Clean data cache by MVA
 135   dsb
 136   mcr     p15,0,R1,c8,c7,1      @ TLBIMVA TLB Invalidate MVA
 137   mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp
 138   dsb
 139   isb
 140   bx      lr
 141
 142 ASM_PFX(ArmInvalidateTlb):
 143   mov     r0,#0
 144   mcr     p15,0,r0,c8,c7,0
 145   mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp
 146   dsb
 147   isb
 148   bx      lr
 149
 150 ASM_PFX(ArmReadNsacr):
 151   mrc     p15, 0, r0, c1, c1, 2
 152   bx      lr
 153
 154 ASM_PFX(ArmWriteNsacr):
 155   mcr     p15, 0, r0, c1, c1, 2
 156   bx      lr
 157
 158 ASM_PFX(ArmReadScr):
 159   mrc     p15, 0, r0, c1, c1, 0
 160   bx      lr
 161
 162 ASM_PFX(ArmWriteScr):
 163   mcr     p15, 0, r0, c1, c1, 0
 164   bx      lr
 165
 166 ASM_PFX(ArmReadHVBar):
 167   mrc     p15, 4, r0, c12, c0, 0
 168   bx      lr
 169
 170 ASM_PFX(ArmWriteHVBar):
 171   mcr     p15, 4, r0, c12, c0, 0
 172   bx      lr
 173
 174
 175 ASM_PFX(ArmReadMVBar):
 176   mrc     p15, 0, r0, c12, c0, 1
 177   bx      lr
 178
 179 ASM_PFX(ArmWriteMVBar):
 180   mcr     p15, 0, r0, c12, c0, 1
 181   bx      lr
 182
 183 ASM_PFX(ArmCallWFE):
 184   wfe
 185   bx      lr
 186
 187 ASM_PFX(ArmCallSEV):
 188   sev
 189   bx      lr
 190
 191 ASM_PFX(ArmReadSctlr):
 192   mrc     p15, 0, R0, c1, c0, 0      @ Read SCTLR into R0 (Read control register configuration data)
 193   bx      lr
 194
 195 ASM_FUNCTION_REMOVE_IF_UNREFERENCED