ArmPkg/Library/ArmLib/Common/ArmLibSupport.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 #include <AsmMacroIoLib.h>
  17
  18 #ifdef ARM_CPU_ARMv6
  19 // No memory barriers for ARMv6
  20 #define isb
  21 #define dsb
  22 #endif
  23
  24 .text
  25 .align 2
  26 GCC_ASM_EXPORT(Cp15IdCode)
  27 GCC_ASM_EXPORT(Cp15CacheInfo)
  28 GCC_ASM_EXPORT(ArmGetInterruptState)
  29 GCC_ASM_EXPORT(ArmGetFiqState)
  30 GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
  31 GCC_ASM_EXPORT(ArmSetTTBR0)
  32 GCC_ASM_EXPORT(ArmSetDomainAccessControl)
  33 GCC_ASM_EXPORT(CPSRMaskInsert)
  34 GCC_ASM_EXPORT(CPSRRead)
  35 GCC_ASM_EXPORT(ArmWriteCPACR)
  36 GCC_ASM_EXPORT(ArmWriteAuxCr)
  37 GCC_ASM_EXPORT(ArmReadAuxCr)
  38 GCC_ASM_EXPORT(ArmInvalidateTlb)
  39 GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
  40 GCC_ASM_EXPORT(ArmWriteNsacr)
  41 GCC_ASM_EXPORT(ArmWriteScr)
  42 GCC_ASM_EXPORT(ArmWriteVMBar)
  43
  44 #------------------------------------------------------------------------------
  45
  46 ASM_PFX(Cp15IdCode):
  47   mrc     p15,0,R0,c0,c0,0
  48   bx      LR
  49
  50 ASM_PFX(Cp15CacheInfo):
  51   mrc     p15,0,R0,c0,c0,1
  52   bx      LR
  53
  54 ASM_PFX(ArmGetInterruptState):
  55   mrs     R0,CPSR
  56   tst     R0,#0x80      @Check if IRQ is enabled.
  57   moveq   R0,#1
  58   movne   R0,#0
  59   bx      LR
  60
  61 ASM_PFX(ArmGetFiqState):
  62   mrs     R0,CPSR
  63   tst     R0,#0x40      @Check if FIQ is enabled.
  64   moveq   R0,#1
  65   movne   R0,#0
  66   bx      LR
  67
  68 ASM_PFX(ArmSetDomainAccessControl):
  69   mcr     p15,0,r0,c3,c0,0
  70   bx      lr
  71
  72 ASM_PFX(CPSRMaskInsert):    @ on entry, r0 is the mask and r1 is the field to insert
  73   stmfd   sp!, {r4-r12, lr} @ save all the banked registers
  74   mov     r3, sp            @ copy the stack pointer into a non-banked register
  75   mrs     r2, cpsr          @ read the cpsr
  76   bic     r2, r2, r0        @ clear mask in the cpsr
  77   and     r1, r1, r0        @ clear bits outside the mask in the input
  78   orr     r2, r2, r1        @ set field
  79   msr     cpsr_cxsf, r2     @ write back cpsr (may have caused a mode switch)
  80   isb
  81   mov     sp, r3            @ restore stack pointer
  82   ldmfd   sp!, {r4-r12, lr} @ restore registers
  83   bx      lr                @ return (hopefully thumb-safe!)             @ return (hopefully thumb-safe!)
  84
  85 ASM_PFX(CPSRRead):
  86   mrs     r0, cpsr
  87   bx      lr
  88
  89 ASM_PFX(ArmWriteCPACR):
  90   mcr     p15, 0, r0, c1, c0, 2
  91   bx      lr
  92
  93 ASM_PFX(ArmWriteAuxCr):
  94   mcr     p15, 0, r0, c1, c0, 1
  95   bx      lr
  96
  97 ASM_PFX(ArmReadAuxCr):
  98   mrc     p15, 0, r0, c1, c0, 1
  99   bx      lr
 100
 101 ASM_PFX(ArmSetTTBR0):
 102   mcr     p15,0,r0,c2,c0,0
 103   isb
 104   bx      lr
 105
 106 ASM_PFX(ArmGetTTBR0BaseAddress):
 107   mrc     p15,0,r0,c2,c0,0
 108   LoadConstantToReg(0xFFFFC000, r1)
 109   and     r0, r0, r1
 110   isb
 111   bx      lr
 112
 113 //
 114 //VOID
 115 //ArmUpdateTranslationTableEntry (
 116 //  IN VOID  *TranslationTableEntry  // R0
 117 //  IN VOID  *MVA                    // R1
 118 //  );
 119 ASM_PFX(ArmUpdateTranslationTableEntry):
 120   mcr     p15,0,R0,c7,c14,1     @ DCCIMVAC Clean data cache by MVA
 121   dsb
 122   mcr     p15,0,R1,c8,c7,1      @ TLBIMVA TLB Invalidate MVA
 123   mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp
 124   dsb
 125   isb
 126   bx      lr
 127
 128 ASM_PFX(ArmInvalidateTlb):
 129   mov     r0,#0
 130   mcr     p15,0,r0,c8,c7,0
 131   mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp
 132   dsb
 133   isb
 134   bx      lr
 135
 136 ASM_PFX(ArmWriteNsacr):
 137   mcr     p15, 0, r0, c1, c1, 2
 138   bx      lr
 139
 140 ASM_PFX(ArmWriteScr):
 141   mcr     p15, 0, r0, c1, c1, 0
 142   bx      lr
 143
 144 ASM_PFX(ArmWriteVMBar):
 145   mcr     p15, 0, r0, c12, c0, 1
 146   bx      lr
 147
 148 ASM_FUNCTION_REMOVE_IF_UNREFERENCED