4d6c253cd211b72f9b10770ac137ca3460e3d0df
[mirror_edk2.git] / ArmPkg / Library / ArmLib / Common / ArmLibSupport.asm
1 //------------------------------------------------------------------------------
2 //
3 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 //
5 // This program and the accompanying materials
6 // are licensed and made available under the terms and conditions of the BSD License
7 // which accompanies this distribution. The full text of the license may be found at
8 // http://opensource.org/licenses/bsd-license.php
9 //
10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 //
13 //------------------------------------------------------------------------------
14
15
16 EXPORT Cp15IdCode
17 EXPORT Cp15CacheInfo
18 EXPORT ArmIsMPCore
19 EXPORT ArmEnableInterrupts
20 EXPORT ArmDisableInterrupts
21 EXPORT ArmGetInterruptState
22 EXPORT ArmEnableFiq
23 EXPORT ArmDisableFiq
24 EXPORT ArmGetFiqState
25 EXPORT ArmInvalidateTlb
26 EXPORT ArmSetTTBR0
27 EXPORT ArmGetTTBR0BaseAddress
28 EXPORT ArmSetDomainAccessControl
29 EXPORT CPSRMaskInsert
30 EXPORT CPSRRead
31
32 AREA ArmLibSupport, CODE, READONLY
33
34 Cp15IdCode
35 mrc p15,0,R0,c0,c0,0
36 bx LR
37
38 Cp15CacheInfo
39 mrc p15,0,R0,c0,c0,1
40 bx LR
41
42 ArmIsMPCore
43 mrc p15,0,R0,c0,c0,5
44 # Get Multiprocessing extension (bit31) & U bit (bit30)
45 and R0, R0, #0xC0000000
46 # if bit30 == 0 then the processor is part of a multiprocessor system)
47 and R0, R0, #0x80000000
48 bx LR
49
50 ArmEnableInterrupts
51 mrs R0,CPSR
52 bic R0,R0,#0x80 ;Enable IRQ interrupts
53 msr CPSR_c,R0
54 bx LR
55
56 ArmDisableInterrupts
57 mrs R0,CPSR
58 orr R1,R0,#0x80 ;Disable IRQ interrupts
59 msr CPSR_c,R1
60 tst R0,#0x80
61 moveq R0,#1
62 movne R0,#0
63 bx LR
64
65 ArmGetInterruptState
66 mrs R0,CPSR
67 tst R0,#0x80 ;Check if IRQ is enabled.
68 moveq R0,#1
69 movne R0,#0
70 bx LR
71
72 ArmEnableFiq
73 mrs R0,CPSR
74 bic R0,R0,#0x40 ;Enable IRQ interrupts
75 msr CPSR_c,R0
76 bx LR
77
78 ArmDisableFiq
79 mrs R0,CPSR
80 orr R1,R0,#0x40 ;Disable IRQ interrupts
81 msr CPSR_c,R1
82 tst R0,#0x40
83 moveq R0,#1
84 movne R0,#0
85 bx LR
86
87 ArmGetFiqState
88 mrs R0,CPSR
89 tst R0,#0x40 ;Check if IRQ is enabled.
90 moveq R0,#1
91 movne R0,#0
92 bx LR
93
94 ArmInvalidateTlb
95 mov r0,#0
96 mcr p15,0,r0,c8,c7,0
97 bx lr
98
99 ArmSetTTBR0
100 mcr p15,0,r0,c2,c0,0
101 bx lr
102
103 ArmGetTTBR0BaseAddress
104 mrc p15,0,r0,c2,c0,0
105 and r0, r0, #0xFFFFC000
106 bx lr
107
108 ArmSetDomainAccessControl
109 mcr p15,0,r0,c3,c0,0
110 bx lr
111
112 CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
113 stmfd sp!, {r4-r12, lr} ; save all the banked registers
114 mov r3, sp ; copy the stack pointer into a non-banked register
115 mrs r2, cpsr ; read the cpsr
116 bic r2, r2, r0 ; clear mask in the cpsr
117 and r1, r1, r0 ; clear bits outside the mask in the input
118 orr r2, r2, r1 ; set field
119 msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
120 mov sp, r3 ; restore stack pointer
121 ldmfd sp!, {r4-r12, lr} ; restore registers
122 bx lr ; return (hopefully thumb-safe!)
123
124 CPSRRead
125 mrs r0, cpsr
126 bx lr
127
128 END
129
130