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[mirror_edk2.git] / ArmPkg / Library / ArmMmuLib / Arm / ArmMmuLibUpdate.c
1 /** @file
2 * File managing the MMU for ARMv7 architecture
3 *
4 * Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
5 *
6 * SPDX-License-Identifier: BSD-2-Clause-Patent
7 *
8 **/
9
10 #include <Uefi.h>
11
12 #include <Library/ArmLib.h>
13 #include <Library/BaseLib.h>
14 #include <Library/BaseMemoryLib.h>
15 #include <Library/DebugLib.h>
16 #include <Library/CacheMaintenanceLib.h>
17 #include <Library/MemoryAllocationLib.h>
18
19 #include <Chipset/ArmV7.h>
20
21 #define __EFI_MEMORY_RWX 0 // no restrictions
22
23 #define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | \
24 EFI_MEMORY_WC | \
25 EFI_MEMORY_WT | \
26 EFI_MEMORY_WB | \
27 EFI_MEMORY_UCE | \
28 EFI_MEMORY_WP)
29
30 STATIC
31 EFI_STATUS
32 ConvertSectionToPages (
33 IN EFI_PHYSICAL_ADDRESS BaseAddress
34 )
35 {
36 UINT32 FirstLevelIdx;
37 UINT32 SectionDescriptor;
38 UINT32 PageTableDescriptor;
39 UINT32 PageDescriptor;
40 UINT32 Index;
41
42 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
43 volatile ARM_PAGE_TABLE_ENTRY *PageTable;
44
45 DEBUG ((DEBUG_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));
46
47 // Obtain page table base
48 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
49
50 // Calculate index into first level translation table for start of modification
51 FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
52 ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
53
54 // Get section attributes and convert to page attributes
55 SectionDescriptor = FirstLevelTable[FirstLevelIdx];
56 PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (SectionDescriptor, FALSE);
57
58 // Allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)
59 PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)AllocatePages (1);
60 if (PageTable == NULL) {
61 return EFI_OUT_OF_RESOURCES;
62 }
63
64 // Write the page table entries out
65 for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {
66 PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS (BaseAddress + (Index << 12)) | PageDescriptor;
67 }
68
69 // Formulate page table entry, Domain=0, NS=0
70 PageTableDescriptor = (((UINTN)PageTable) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
71
72 // Write the page table entry out, replacing section entry
73 FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;
74
75 return EFI_SUCCESS;
76 }
77
78 STATIC
79 EFI_STATUS
80 UpdatePageEntries (
81 IN EFI_PHYSICAL_ADDRESS BaseAddress,
82 IN UINT64 Length,
83 IN UINT64 Attributes,
84 OUT BOOLEAN *FlushTlbs OPTIONAL
85 )
86 {
87 EFI_STATUS Status;
88 UINT32 EntryValue;
89 UINT32 EntryMask;
90 UINT32 FirstLevelIdx;
91 UINT32 Offset;
92 UINT32 NumPageEntries;
93 UINT32 Descriptor;
94 UINT32 p;
95 UINT32 PageTableIndex;
96 UINT32 PageTableEntry;
97 UINT32 CurrentPageTableEntry;
98 VOID *Mva;
99
100 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
101 volatile ARM_PAGE_TABLE_ENTRY *PageTable;
102
103 Status = EFI_SUCCESS;
104
105 // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
106 // EntryValue: values at bit positions specified by EntryMask
107 EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK;
108 if ((Attributes & EFI_MEMORY_XP) != 0) {
109 EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN;
110 } else {
111 EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE;
112 }
113
114 // Although the PI spec is unclear on this, the GCD guarantees that only
115 // one Attribute bit is set at a time, so the order of the conditionals below
116 // is irrelevant. If no memory attribute is specified, we preserve whatever
117 // memory type is set in the page tables, and update the permission attributes
118 // only.
119 if ((Attributes & EFI_MEMORY_UC) != 0) {
120 // modify cacheability attributes
121 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
122 // map to strongly ordered
123 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
124 } else if ((Attributes & EFI_MEMORY_WC) != 0) {
125 // modify cacheability attributes
126 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
127 // map to normal non-cacheable
128 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
129 } else if ((Attributes & EFI_MEMORY_WT) != 0) {
130 // modify cacheability attributes
131 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
132 // write through with no-allocate
133 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0
134 } else if ((Attributes & EFI_MEMORY_WB) != 0) {
135 // modify cacheability attributes
136 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
137 // write back (with allocate)
138 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1
139 } else if ((Attributes & CACHE_ATTRIBUTE_MASK) != 0) {
140 // catch unsupported memory type attributes
141 ASSERT (FALSE);
142 return EFI_UNSUPPORTED;
143 }
144
145 if ((Attributes & EFI_MEMORY_RO) != 0) {
146 EntryValue |= TT_DESCRIPTOR_PAGE_AP_RO_RO;
147 } else {
148 EntryValue |= TT_DESCRIPTOR_PAGE_AP_RW_RW;
149 }
150
151 // Obtain page table base
152 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
153
154 // Calculate number of 4KB page table entries to change
155 NumPageEntries = (UINT32)(Length / TT_DESCRIPTOR_PAGE_SIZE);
156
157 // Iterate for the number of 4KB pages to change
158 Offset = 0;
159 for (p = 0; p < NumPageEntries; p++) {
160 // Calculate index into first level translation table for page table value
161
162 FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
163 ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
164
165 // Read the descriptor from the first level page table
166 Descriptor = FirstLevelTable[FirstLevelIdx];
167
168 // Does this descriptor need to be converted from section entry to 4K pages?
169 if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (Descriptor)) {
170 Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
171 if (EFI_ERROR (Status)) {
172 // Exit for loop
173 break;
174 }
175
176 // Re-read descriptor
177 Descriptor = FirstLevelTable[FirstLevelIdx];
178 if (FlushTlbs != NULL) {
179 *FlushTlbs = TRUE;
180 }
181 }
182
183 // Obtain page table base address
184 PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS (Descriptor);
185
186 // Calculate index into the page table
187 PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
188 ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);
189
190 // Get the entry
191 CurrentPageTableEntry = PageTable[PageTableIndex];
192
193 // Mask off appropriate fields
194 PageTableEntry = CurrentPageTableEntry & ~EntryMask;
195
196 // Mask in new attributes and/or permissions
197 PageTableEntry |= EntryValue;
198
199 if (CurrentPageTableEntry != PageTableEntry) {
200 Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT));
201
202 // Only need to update if we are changing the entry
203 PageTable[PageTableIndex] = PageTableEntry;
204 ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);
205 }
206
207 Status = EFI_SUCCESS;
208 Offset += TT_DESCRIPTOR_PAGE_SIZE;
209 } // End first level translation table loop
210
211 return Status;
212 }
213
214 STATIC
215 EFI_STATUS
216 UpdateSectionEntries (
217 IN EFI_PHYSICAL_ADDRESS BaseAddress,
218 IN UINT64 Length,
219 IN UINT64 Attributes
220 )
221 {
222 EFI_STATUS Status;
223 UINT32 EntryMask;
224 UINT32 EntryValue;
225 UINT32 FirstLevelIdx;
226 UINT32 NumSections;
227 UINT32 i;
228 UINT32 CurrentDescriptor;
229 UINT32 Descriptor;
230 VOID *Mva;
231 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
232
233 Status = EFI_SUCCESS;
234
235 // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
236 // EntryValue: values at bit positions specified by EntryMask
237
238 // Make sure we handle a section range that is unmapped
239 EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK | TT_DESCRIPTOR_SECTION_XN_MASK |
240 TT_DESCRIPTOR_SECTION_AP_MASK;
241 EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION;
242
243 // Although the PI spec is unclear on this, the GCD guarantees that only
244 // one Attribute bit is set at a time, so the order of the conditionals below
245 // is irrelevant. If no memory attribute is specified, we preserve whatever
246 // memory type is set in the page tables, and update the permission attributes
247 // only.
248 if ((Attributes & EFI_MEMORY_UC) != 0) {
249 // modify cacheability attributes
250 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
251 // map to strongly ordered
252 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
253 } else if ((Attributes & EFI_MEMORY_WC) != 0) {
254 // modify cacheability attributes
255 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
256 // map to normal non-cacheable
257 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
258 } else if ((Attributes & EFI_MEMORY_WT) != 0) {
259 // modify cacheability attributes
260 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
261 // write through with no-allocate
262 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0
263 } else if ((Attributes & EFI_MEMORY_WB) != 0) {
264 // modify cacheability attributes
265 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
266 // write back (with allocate)
267 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1
268 } else if ((Attributes & CACHE_ATTRIBUTE_MASK) != 0) {
269 // catch unsupported memory type attributes
270 ASSERT (FALSE);
271 return EFI_UNSUPPORTED;
272 }
273
274 if ((Attributes & EFI_MEMORY_RO) != 0) {
275 EntryValue |= TT_DESCRIPTOR_SECTION_AP_RO_RO;
276 } else {
277 EntryValue |= TT_DESCRIPTOR_SECTION_AP_RW_RW;
278 }
279
280 if ((Attributes & EFI_MEMORY_XP) != 0) {
281 EntryValue |= TT_DESCRIPTOR_SECTION_XN_MASK;
282 }
283
284 // obtain page table base
285 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
286
287 // calculate index into first level translation table for start of modification
288 FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
289 ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
290
291 // calculate number of 1MB first level entries this applies to
292 NumSections = (UINT32)(Length / TT_DESCRIPTOR_SECTION_SIZE);
293
294 // iterate through each descriptor
295 for (i = 0; i < NumSections; i++) {
296 CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];
297
298 // has this descriptor already been converted to pages?
299 if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (CurrentDescriptor)) {
300 // forward this 1MB range to page table function instead
301 Status = UpdatePageEntries (
302 (FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT,
303 TT_DESCRIPTOR_SECTION_SIZE,
304 Attributes,
305 NULL
306 );
307 } else {
308 // still a section entry
309
310 if (CurrentDescriptor != 0) {
311 // mask off appropriate fields
312 Descriptor = CurrentDescriptor & ~EntryMask;
313 } else {
314 Descriptor = ((UINTN)FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT;
315 }
316
317 // mask in new attributes and/or permissions
318 Descriptor |= EntryValue;
319
320 if (CurrentDescriptor != Descriptor) {
321 Mva = (VOID *)(UINTN)(((UINTN)FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
322
323 // Only need to update if we are changing the descriptor
324 FirstLevelTable[FirstLevelIdx + i] = Descriptor;
325 ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);
326 }
327
328 Status = EFI_SUCCESS;
329 }
330 }
331
332 return Status;
333 }
334
335 EFI_STATUS
336 ArmSetMemoryAttributes (
337 IN EFI_PHYSICAL_ADDRESS BaseAddress,
338 IN UINT64 Length,
339 IN UINT64 Attributes
340 )
341 {
342 EFI_STATUS Status;
343 UINT64 ChunkLength;
344 BOOLEAN FlushTlbs;
345
346 if (BaseAddress > (UINT64)MAX_ADDRESS) {
347 return EFI_UNSUPPORTED;
348 }
349
350 Length = MIN (Length, (UINT64)MAX_ADDRESS - BaseAddress + 1);
351 if (Length == 0) {
352 return EFI_SUCCESS;
353 }
354
355 FlushTlbs = FALSE;
356 while (Length > 0) {
357 if ((BaseAddress % TT_DESCRIPTOR_SECTION_SIZE == 0) &&
358 (Length >= TT_DESCRIPTOR_SECTION_SIZE))
359 {
360 ChunkLength = Length - Length % TT_DESCRIPTOR_SECTION_SIZE;
361
362 DEBUG ((
363 DEBUG_PAGE,
364 "SetMemoryAttributes(): MMU section 0x%lx length 0x%lx to %lx\n",
365 BaseAddress,
366 ChunkLength,
367 Attributes
368 ));
369
370 Status = UpdateSectionEntries (BaseAddress, ChunkLength, Attributes);
371
372 FlushTlbs = TRUE;
373 } else {
374 //
375 // Process page by page until the next section boundary, but only if
376 // we have more than a section's worth of area to deal with after that.
377 //
378 ChunkLength = TT_DESCRIPTOR_SECTION_SIZE -
379 (BaseAddress % TT_DESCRIPTOR_SECTION_SIZE);
380 if (ChunkLength + TT_DESCRIPTOR_SECTION_SIZE > Length) {
381 ChunkLength = Length;
382 }
383
384 DEBUG ((
385 DEBUG_PAGE,
386 "SetMemoryAttributes(): MMU page 0x%lx length 0x%lx to %lx\n",
387 BaseAddress,
388 ChunkLength,
389 Attributes
390 ));
391
392 Status = UpdatePageEntries (
393 BaseAddress,
394 ChunkLength,
395 Attributes,
396 &FlushTlbs
397 );
398 }
399
400 if (EFI_ERROR (Status)) {
401 break;
402 }
403
404 BaseAddress += ChunkLength;
405 Length -= ChunkLength;
406 }
407
408 if (FlushTlbs) {
409 ArmInvalidateTlb ();
410 }
411
412 return Status;
413 }
414
415 EFI_STATUS
416 ArmSetMemoryRegionNoExec (
417 IN EFI_PHYSICAL_ADDRESS BaseAddress,
418 IN UINT64 Length
419 )
420 {
421 return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_XP);
422 }
423
424 EFI_STATUS
425 ArmClearMemoryRegionNoExec (
426 IN EFI_PHYSICAL_ADDRESS BaseAddress,
427 IN UINT64 Length
428 )
429 {
430 return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX);
431 }
432
433 EFI_STATUS
434 ArmSetMemoryRegionReadOnly (
435 IN EFI_PHYSICAL_ADDRESS BaseAddress,
436 IN UINT64 Length
437 )
438 {
439 return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO);
440 }
441
442 EFI_STATUS
443 ArmClearMemoryRegionReadOnly (
444 IN EFI_PHYSICAL_ADDRESS BaseAddress,
445 IN UINT64 Length
446 )
447 {
448 return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX);
449 }
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