2 Differentiated System Description Table Fields (SSDT)
4 Copyright (c) 2014-2015, ARM Ltd. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include "ArmPlatform.h"
18 See Reference [1] 6.2.12
19 "There are two ways that _PRT can be used. ...
20 In the second model, the PCI interrupts are hardwired to specific interrupt
21 inputs on the interrupt controller and are not configurable. In this case,
22 the Source field in _PRT does not reference a device, but instead contains
23 the value zero, and the Source Index field contains the global system
24 interrupt to which the PCI interrupt is hardwired."
26 #define PRT_ENTRY(Address, Pin, Interrupt) \
28 Address, /* uses the same format as _ADR */ \
29 Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \
30 Zero, /* allocated from the global interrupt pool. */ \
31 Interrupt /* global system interrupt number */ \
35 See Reference [1] 6.1.1
36 "High word–Device #, Low word–Function #. (for example, device 3, function 2 is
37 0x00030002). To refer to all the functions on a device #, use a function number of FFFF)."
39 #define ROOT_PRT_ENTRY(Pin, Interrupt) PRT_ENTRY(0x0000FFFF, Pin, Interrupt)
40 // Device 0 for Bridge.
43 DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {
50 Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
51 Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
52 Name(_SEG, Zero) // PCI Segment Group number
53 Name(_BBN, Zero) // PCI Base Bus Number
57 Name(_ADR, 0xF0000000) // Dev 0, Func 0
61 Name(_PRT, Package() {
62 ROOT_PRT_ENTRY(0, 168), // INTA
63 ROOT_PRT_ENTRY(1, 169), // INTB
64 ROOT_PRT_ENTRY(2, 170), // INTC
65 ROOT_PRT_ENTRY(3, 171), // INTD
67 // Root complex resources
68 Method (_CRS, 0, Serialized) {
69 Name (RBUF, ResourceTemplate () {
70 WordBusNumber ( // Bus numbers assigned to this root
72 MinFixed, MaxFixed, PosDecode,
73 0, // AddressGranularity
74 0, // AddressMinimum - Minimum Bus Number
75 255, // AddressMaximum - Maximum Bus Number
76 0, // AddressTranslation - Set to 0
77 256 // RangeLength - Number of Busses
80 DWordMemory ( // 32-bit BAR Windows
81 ResourceProducer, PosDecode,
84 0x00000000, // Granularity
85 0x50000000, // Min Base Address
86 0x57FFFFFF, // Max Base Address
87 0x00000000, // Translate
91 QWordMemory ( // 64-bit BAR Windows
92 ResourceProducer, PosDecode,
95 0x00000000, // Granularity
96 0x4000000000, // Min Base Address
97 0x40FFFFFFFF, // Max Base Address
98 0x00000000, // Translate
102 DWordIo ( // IO window
108 0x00000000, // Granularity
109 0x5f800000, // Min Base Address
110 0x5fffffff, // Max Base Address
111 0x5f800000, // Translate
120 // OS Control Handoff
122 Name(SUPP, Zero) // PCI _OSC Support Field value
123 Name(CTRL, Zero) // PCI _OSC Control Field value
126 See [1] 6.2.10, [2] 4.5
129 // Check for proper UUID
130 If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
131 // Create DWord-adressable fields from the Capabilities Buffer
132 CreateDWordField(Arg3,0,CDW1)
133 CreateDWordField(Arg3,4,CDW2)
134 CreateDWordField(Arg3,8,CDW3)
136 // Save Capabilities DWord2 & 3
140 // Only allow native hot plug control if OS supports:
144 If(LNotEqual(And(SUPP, 0x16), 0x16)) {
145 And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
148 // Always allow native PME, AER (no dependencies)
150 // Never allow SHPC (no SHPC controller in this system)
154 If(LNot(And(CDW1,1))) { // Query flag clear?
155 // Disable GPEs for features granted native control.
156 If(And(CTRL,0x01)) { // Hot plug control granted?
157 Store(0,HPCE) // clear the hot plug SCI enable bit
158 Store(1,HPCS) // clear the hot plug SCI status bit
160 If(And(CTRL,0x04)) { // PME control granted?
161 Store(0,PMCE) // clear the PME SCI enable bit
162 Store(1,PMCS) // clear the PME SCI status bit
164 If(And(CTRL,0x10)) { // OS restoring PCIe cap structure?
165 // Set status to not restore PCIe cap structure
166 // upon resume from S3
172 If(LNotEqual(Arg1,One)) { // Unknown revision
176 If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
179 // Update DWORD3 in the buffer
183 Or(CDW1,4,CDW1) // Unrecognized UUID