ArmPlatformPkg/ArmJunoPkg/AcpiTables/AcpiSsdtRootPci.asl

   1 /** @file
   2   Differentiated System Description Table Fields (SSDT)
   3
   4   Copyright (c) 2014-2015, ARM Ltd. All rights reserved.<BR>
   5     This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include "ArmPlatform.h"
  16
  17 /*
  18   See Reference [1] 6.2.12
  19   "There are two ways that _PRT can be used. ...
  20   In the second model, the PCI interrupts are hardwired to specific interrupt
  21   inputs on the interrupt controller and are not configurable. In this case,
  22   the Source field in _PRT does not reference a device, but instead contains
  23   the value zero, and the Source Index field contains the global system
  24   interrupt to which the PCI interrupt is hardwired."
  25 */
  26 #define PRT_ENTRY(Address, Pin, Interrupt)                                                       \
  27           Package (4) {                                                                           \
  28             Address,    /* uses the same format as _ADR */                                        \
  29             Pin,        /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */  \
  30             Zero,       /* allocated from the global interrupt pool. */                           \
  31             Interrupt   /* global system interrupt number */                                      \
  32           }
  33
  34 /*
  35   See Reference [1] 6.1.1
  36   "High word–Device #, Low word–Function #. (for example, device 3, function 2 is
  37    0x00030002). To refer to all the functions on a device #, use a function number of FFFF)."
  38 */
  39 #define ROOT_PRT_ENTRY(Pin, Interrupt)   PRT_ENTRY(0x0000FFFF, Pin, Interrupt)
  40                                                     // Device 0 for Bridge.
  41
  42
  43 DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {
  44   Scope(_SB) {
  45         //
  46         // PCI Root Complex
  47         //
  48         Device(PCI0)
  49     {
  50                 Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
  51                 Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
  52                 Name(_SEG, Zero) // PCI Segment Group number
  53                 Name(_BBN, Zero) // PCI Base Bus Number
  54
  55         // Root Complex 0
  56         Device (RP0) {
  57             Name(_ADR, 0xF0000000)    // Dev 0, Func 0
  58         }
  59
  60         // PCI Routing Table
  61                 Name(_PRT, Package() {
  62                 ROOT_PRT_ENTRY(0, 136),   // INTA
  63                 ROOT_PRT_ENTRY(1, 137),   // INTB
  64                 ROOT_PRT_ENTRY(2, 138),   // INTC
  65                 ROOT_PRT_ENTRY(3, 139),   // INTD
  66         })
  67         // Root complex resources
  68                 Method (_CRS, 0, Serialized) {
  69                         Name (RBUF, ResourceTemplate () {
  70                                 WordBusNumber ( // Bus numbers assigned to this root
  71                                         ResourceProducer,
  72                                         MinFixed, MaxFixed, PosDecode,
  73                                         0,   // AddressGranularity
  74                                         0,   // AddressMinimum - Minimum Bus Number
  75                                         255, // AddressMaximum - Maximum Bus Number
  76                                         0,   // AddressTranslation - Set to 0
  77                                         256  // RangeLength - Number of Busses
  78                                 )
  79
  80                                 DWordMemory ( // 32-bit BAR Windows
  81                                         ResourceProducer, PosDecode,
  82                                         MinFixed, MaxFixed,
  83                                         Cacheable, ReadWrite,
  84                                         0x00000000,                                                     // Granularity
  85                                         0x50000000,                                                     // Min Base Address
  86                                         0x57FFFFFF,                                                     // Max Base Address
  87                                         0x00000000,                                                     // Translate
  88                                         0x08000000                                                              // Length
  89                                 )
  90
  91                                 QWordMemory ( // 64-bit BAR Windows
  92                                         ResourceProducer, PosDecode,
  93                                         MinFixed, MaxFixed,
  94                                         Cacheable, ReadWrite,
  95                                         0x00000000,                                                     // Granularity
  96                                         0x4000000000,                                                   // Min Base Address
  97                                         0x40FFFFFFFF,                                                   // Max Base Address
  98                                         0x00000000,                                                     // Translate
  99                                         0x100000000                                                             // Length
 100                                 )
 101                         }) // Name(RBUF)
 102
 103                         Return (RBUF)
 104                 } // Method(_CRS)
 105
 106                 //
 107                 // OS Control Handoff
 108                 //
 109                 Name(SUPP, Zero) // PCI _OSC Support Field value
 110                 Name(CTRL, Zero) // PCI _OSC Control Field value
 111
 112                 /*
 113           See [1] 6.2.10, [2] 4.5
 114                 */
 115                 Method(_OSC,4) {
 116                         // Check for proper UUID
 117                         If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
 118                                 // Create DWord-adressable fields from the Capabilities Buffer
 119                                 CreateDWordField(Arg3,0,CDW1)
 120                                 CreateDWordField(Arg3,4,CDW2)
 121                                 CreateDWordField(Arg3,8,CDW3)
 122
 123                                 // Save Capabilities DWord2 & 3
 124                                 Store(CDW2,SUPP)
 125                                 Store(CDW3,CTRL)
 126
 127                                 // Only allow native hot plug control if OS supports:
 128                                 // * ASPM
 129                                 // * Clock PM
 130                                 // * MSI/MSI-X
 131                                 If(LNotEqual(And(SUPP, 0x16), 0x16)) {
 132                                         And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
 133                                 }
 134
 135                                 // Always allow native PME, AER (no dependencies)
 136
 137                                 // Never allow SHPC (no SHPC controller in this system)
 138                                 And(CTRL,0x1D,CTRL)
 139
 140 #if 0
 141                                 If(LNot(And(CDW1,1))) {         // Query flag clear?
 142                                         // Disable GPEs for features granted native control.
 143                                         If(And(CTRL,0x01)) {    // Hot plug control granted?
 144                                                 Store(0,HPCE)           // clear the hot plug SCI enable bit
 145                                                 Store(1,HPCS)           // clear the hot plug SCI status bit
 146                                         }
 147                                         If(And(CTRL,0x04)) {    // PME control granted?
 148                                                 Store(0,PMCE)           // clear the PME SCI enable bit
 149                                                 Store(1,PMCS)           // clear the PME SCI status bit
 150                                         }
 151                                         If(And(CTRL,0x10)) {    // OS restoring PCIe cap structure?
 152                                                 // Set status to not restore PCIe cap structure
 153                                                 // upon resume from S3
 154                                                 Store(1,S3CR)
 155                                         }
 156                                 }
 157 #endif
 158
 159                                 If(LNotEqual(Arg1,One)) {       // Unknown revision
 160                                         Or(CDW1,0x08,CDW1)
 161                                 }
 162
 163                                 If(LNotEqual(CDW3,CTRL)) {      // Capabilities bits were masked
 164                                         Or(CDW1,0x10,CDW1)
 165                                 }
 166                                 // Update DWORD3 in the buffer
 167                                 Store(CTRL,CDW3)
 168                                 Return(Arg3)
 169                         } Else {
 170                                 Or(CDW1,4,CDW1) // Unrecognized UUID
 171                                 Return(Arg3)
 172                         }
 173                 } // End _OSC
 174     } // PCI0
 175   }
 176 }