3 * Copyright (c) 2011, ARM Limited. All rights reserved.
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include <Library/IoLib.h>
16 #include <Library/ArmPlatformLib.h>
17 #include <Library/DebugLib.h>
18 #include <Library/PcdLib.h>
20 #include <Drivers/PL341Dmc.h>
21 #include <Drivers/SP804Timer.h>
23 #include <Ppi/ArmMpCoreInfo.h>
25 #include <ArmPlatform.h>
27 ARM_CORE_INFO mRealViewEbMpCoreInfoTable
[] = {
32 // MP Core MailBox Set/Get/Clear Addresses and Clear Value
33 (EFI_PHYSICAL_ADDRESS
)ARM_EB_SYS_FLAGS_REG
,
34 (EFI_PHYSICAL_ADDRESS
)ARM_EB_SYS_FLAGS_SET_REG
,
35 (EFI_PHYSICAL_ADDRESS
)ARM_EB_SYS_FLAGS_CLR_REG
,
42 // MP Core MailBox Set/Get/Clear Addresses and Clear Value
43 (EFI_PHYSICAL_ADDRESS
)ARM_EB_SYS_FLAGS_REG
,
44 (EFI_PHYSICAL_ADDRESS
)ARM_EB_SYS_FLAGS_SET_REG
,
45 (EFI_PHYSICAL_ADDRESS
)ARM_EB_SYS_FLAGS_CLR_REG
,
51 Remap the memory at 0x0
53 Some platform requires or gives the ability to remap the memory at the address 0x0.
54 This function can do nothing if this feature is not relevant to your platform.
58 ArmPlatformBootRemapping (
62 // Disable memory remapping and return to normal mapping
63 MmioOr32 (ARM_EB_SYSCTRL
, BIT8
); //EB_SP810_CTRL_BASE
67 Return the current Boot Mode
69 This function returns the boot reason on the platform
73 ArmPlatformGetBootMode (
77 return BOOT_WITH_FULL_CONFIGURATION
;
81 Initialize controllers that must setup in the normal world
83 This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
88 ArmPlatformNormalInitialize (
92 // Configure periodic timer (TIMER0) for 1MHz operation
93 MmioOr32 (SP810_CTRL_BASE
+ SP810_SYS_CTRL_REG
, SP810_SYS_CTRL_TIMER0_TIMCLK
);
94 // Configure 1MHz clock
95 MmioOr32 (SP810_CTRL_BASE
+ SP810_SYS_CTRL_REG
, SP810_SYS_CTRL_TIMER1_TIMCLK
);
96 // configure SP810 to use 1MHz clock and disable
97 MmioAndThenOr32 (SP810_CTRL_BASE
+ SP810_SYS_CTRL_REG
, ~SP810_SYS_CTRL_TIMER2_EN
, SP810_SYS_CTRL_TIMER2_TIMCLK
);
98 // Configure SP810 to use 1MHz clock and disable
99 MmioAndThenOr32 (SP810_CTRL_BASE
+ SP810_SYS_CTRL_REG
, ~SP810_SYS_CTRL_TIMER3_EN
, SP810_SYS_CTRL_TIMER3_TIMCLK
);
103 Initialize the system (or sometimes called permanent) memory
105 This memory is generally represented by the DRAM.
109 ArmPlatformInitializeSystemMemory (
113 // We do not need to initialize the System Memory on RTSM
117 PrePeiCoreGetMpCoreInfo (
118 OUT UINTN
*CoreCount
,
119 OUT ARM_CORE_INFO
**ArmCoreTable
122 if ((MmioRead32 (ARM_EB_SYS_PROCID0_REG
) & ARM_EB_SYS_PROC_ID_MASK
) == ARM_EB_SYS_PROC_ID_CORTEX_A9
) {
123 *CoreCount
= sizeof(mRealViewEbMpCoreInfoTable
) / sizeof(ARM_CORE_INFO
);
124 *ArmCoreTable
= mRealViewEbMpCoreInfoTable
;
127 return EFI_UNSUPPORTED
;
131 // Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
132 EFI_GUID mArmMpCoreInfoPpiGuid
= ARM_MP_CORE_INFO_PPI_GUID
;
133 ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi
= { PrePeiCoreGetMpCoreInfo
};
135 EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable
[] = {
137 EFI_PEI_PPI_DESCRIPTOR_PPI
,
138 &mArmMpCoreInfoPpiGuid
,
144 ArmPlatformGetPlatformPpiList (
145 OUT UINTN
*PpiListSize
,
146 OUT EFI_PEI_PPI_DESCRIPTOR
**PpiList
149 *PpiListSize
= sizeof(gPlatformPpiTable
);
150 *PpiList
= gPlatformPpiTable
;