ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15-A7/ArmPlatform.h

   1 /** @file
   2 *  Header defining Versatile Express constants (Base addresses, sizes, flags)
   3 *
   4 *  Copyright (c) 2012, ARM Limited. All rights reserved.
   5 *
   6 *  This program and the accompanying materials
   7 *  are licensed and made available under the terms and conditions of the BSD License
   8 *  which accompanies this distribution.  The full text of the license may be found at
   9 *  http://opensource.org/licenses/bsd-license.php
  10 *
  11 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 *
  14 **/
  15
  16 #ifndef __ARM_VEXPRESS_CTA15A7_H__
  17 #define __ARM_VEXPRESS_CTA15A7_H__
  18
  19 #include <VExpressMotherBoard.h>
  20
  21 /***********************************************************************************
  22 // Platform Memory Map
  23 ************************************************************************************/
  24
  25 // Motherboard Peripheral and On-chip peripheral
  26 #define ARM_VE_BOARD_PERIPH_BASE              0x1C010000
  27
  28 #ifdef ARM_BIGLITTLE_TC2
  29
  30 // Secure NOR Flash
  31 #define ARM_VE_SEC_NOR0_BASE                  0x00000000
  32 #define ARM_VE_SEC_NOR0_SZ                    SIZE_64MB
  33
  34 // Secure RAM
  35 #define ARM_VE_SEC_RAM0_BASE                  0x04000000
  36 #define ARM_VE_SEC_RAM0_SZ                    SIZE_64MB
  37
  38 #endif
  39
  40 // NOR Flash 0
  41 #define ARM_VE_SMB_NOR0_BASE                  0x08000000
  42 #define ARM_VE_SMB_NOR0_SZ                    SIZE_64MB
  43 // NOR Flash 1
  44 #define ARM_VE_SMB_NOR1_BASE                  0x0C000000
  45 #define ARM_VE_SMB_NOR1_SZ                    SIZE_64MB
  46
  47 // SRAM
  48 #define ARM_VE_SMB_SRAM_BASE                  0x14000000
  49 #define ARM_VE_SMB_SRAM_SZ                    SIZE_32MB
  50
  51 // USB, Ethernet, VRAM
  52 #ifdef ARM_BIGLITTLE_TC2
  53 #define ARM_VE_SMB_PERIPH_BASE                0x18000000
  54 #define ARM_VE_SMB_PERIPH_SZ                  (SIZE_64MB + SIZE_32MB + SIZE_16MB)
  55 #else
  56 #define ARM_VE_SMB_PERIPH_BASE                0x1C000000
  57 #define ARM_VE_SMB_PERIPH_SZ                  (SIZE_64MB + SIZE_16MB)
  58 #endif
  59 #define PL111_CLCD_VRAM_MOTHERBOARD_BASE      ARM_VE_SMB_PERIPH_BASE
  60
  61 // On-Chip non-secure ROM
  62 #ifdef ARM_BIGLITTLE_TC2
  63 #define ARM_VE_TC2_NON_SECURE_ROM_BASE        0x1F000000
  64 #define ARM_VE_TC2_NON_SECURE_ROM_SZ          SIZE_16MB
  65 #endif
  66
  67 // On-Chip Peripherals
  68 #define ARM_VE_ONCHIP_PERIPH_BASE             0x20000000
  69 #define ARM_VE_ONCHIP_PERIPH_SZ               0x10000000
  70
  71 // On-Chip non-secure SRAM
  72 #ifdef ARM_BIGLITTLE_TC2
  73 #define ARM_VE_TC2_NON_SECURE_SRAM_BASE       0x2E000000
  74 #define ARM_VE_TC2_NON_SECURE_SRAM_SZ         SIZE_64KB
  75 #endif
  76
  77 // Allocate a section for the VRAM (Video RAM)
  78 // If 0 then allow random memory allocation
  79 #define LCD_VRAM_CORE_TILE_BASE               0
  80
  81 // Define SEC phase sync point
  82 #define ARM_SEC_EVENT_BOOT_IMAGE_TABLE_IS_AVAILABLE   (ARM_SEC_EVENT_MAX + 1)
  83
  84 /***********************************************************************************
  85    Core Tile memory-mapped Peripherals
  86 ************************************************************************************/
  87
  88 // PL354 Static Memory Controller Base
  89 #ifdef ARM_BIGLITTLE_TC2
  90 #define ARM_VE_SMC_CTRL_BASE                    0x7FFD0000
  91 #else
  92 #define ARM_VE_SMC_CTRL_BASE                    (ARM_VE_BOARD_PERIPH_BASE + 0xE1000)
  93 #endif
  94
  95 #define ARM_CTA15A7_SCC_BASE                    0x7FFF0000
  96 #define ARM_CTA15A7_SCC_CFGREG48                (ARM_CTA15A7_SCC_BASE + 0x700)
  97
  98 #define ARM_CTA15A7_SCC_SYSINFO                 ARM_CTA15A7_SCC_CFGREG48
  99
 100 #define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A7_NUM_CPU(val)   (((val) >> 20) & 0xF)
 101 #define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A15_NUM_CPU(val)  (((val) >> 16) & 0xF)
 102 #define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A15        (1 << 0)
 103 #define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A7         (1 << 1)
 104
 105 #define ARM_CTA15A7_SPC_BASE                    0x7FFF0B00
 106 #define ARM_CTA15A7_SPC_WAKE_INT_MASK           (ARM_CTA15A7_SPC_BASE + 0x24)
 107 #define ARM_CTA15A7_SPC_STANDBYWFI_STAT         (ARM_CTA15A7_SPC_BASE + 0x3C)
 108 #define ARM_CTA15A7_SPC_A15_BX_ADDR0            (ARM_CTA15A7_SPC_BASE + 0x68)
 109 #define ARM_CTA15A7_SPC_A15_BX_ADDR1            (ARM_CTA15A7_SPC_BASE + 0x6C)
 110 #define ARM_CTA15A7_SPC_A15_BX_ADDR2            (ARM_CTA15A7_SPC_BASE + 0x70)
 111 #define ARM_CTA15A7_SPC_A15_BX_ADDR3            (ARM_CTA15A7_SPC_BASE + 0x74)
 112 #define ARM_CTA15A7_SPC_A7_BX_ADDR0             (ARM_CTA15A7_SPC_BASE + 0x78)
 113 #define ARM_CTA15A7_SPC_A7_BX_ADDR1             (ARM_CTA15A7_SPC_BASE + 0x7C)
 114 #define ARM_CTA15A7_SPC_A7_BX_ADDR2             (ARM_CTA15A7_SPC_BASE + 0x80)
 115 #define ARM_CTA15A7_SPC_A7_BX_ADDR3             (ARM_CTA15A7_SPC_BASE + 0x84)
 116
 117 #define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_0  (1 << 0)
 118 #define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_1  (1 << 1)
 119 #define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_0  (1 << 2)
 120 #define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_1  (1 << 3)
 121 #define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_0   (1 << 4)
 122 #define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_1   (1 << 5)
 123 #define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_2   (1 << 6)
 124 #define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_0   (1 << 7)
 125 #define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_1   (1 << 8)
 126 #define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_2   (1 << 9)
 127
 128 #define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_0   (1 << 0)
 129 #define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_1   (1 << 1)
 130 #define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_L2  (1 << 2)
 131 #define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_0    (1 << 3)
 132 #define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_1    (1 << 4)
 133 #define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_2    (1 << 5)
 134 #define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_L2   (1 << 6)
 135
 136
 137 /***********************************************************************************
 138 // Memory-mapped peripherals
 139 ************************************************************************************/
 140
 141 /*// SP810 Controller
 142 #undef SP810_CTRL_BASE
 143 #define SP810_CTRL_BASE                         0x1C020000
 144
 145 // PL111 Colour LCD Controller
 146 #define PL111_CLCD_SITE                         ARM_VE_MOTHERBOARD_SITE
 147 #define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID  1
 148 #define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID  1
 149
 150 // VRAM offset for the PL111 Colour LCD Controller on the motherboard
 151 #define VRAM_MOTHERBOARD_BASE                     (ARM_VE_SMB_PERIPH_BASE   + 0x00000)*/
 152
 153 #endif