ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4/ArmPlatform.h

   1 /** @file
   2 *  Header defining Versatile Express constants (Base addresses, sizes, flags)
   3 *
   4 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   5 *
   6 *  This program and the accompanying materials
   7 *  are licensed and made available under the terms and conditions of the BSD License
   8 *  which accompanies this distribution.  The full text of the license may be found at
   9 *  http://opensource.org/licenses/bsd-license.php
  10 *
  11 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 *
  14 **/
  15
  16 #ifndef __ARM_VEXPRESS_H__
  17 #define __ARM_VEXPRESS_H__
  18
  19 #include <Base.h>
  20 #include <VExpressMotherBoard.h>
  21
  22 /***********************************************************************************
  23 // Platform Memory Map
  24 ************************************************************************************/
  25
  26 // Can be NOR0, NOR1, DRAM
  27 #define ARM_VE_REMAP_BASE                       0x00000000
  28 #define ARM_VE_REMAP_SZ                         SIZE_64MB
  29
  30 // Motherboard Peripheral and On-chip peripheral
  31 #define ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE       0x10000000
  32 #define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ         SIZE_256MB
  33 #define ARM_VE_BOARD_PERIPH_BASE                0x10000000
  34 #define ARM_VE_CHIP_PERIPH_BASE                 0x10020000
  35
  36 // SMC
  37 #define ARM_VE_SMC_BASE                         0x40000000
  38 #define ARM_VE_SMC_SZ                           0x1C000000
  39
  40 // NOR Flash 1
  41 #define ARM_VE_SMB_NOR0_BASE                    0x40000000
  42 #define ARM_VE_SMB_NOR0_SZ                      SIZE_64MB
  43 // NOR Flash 2
  44 #define ARM_VE_SMB_NOR1_BASE                    0x44000000
  45 #define ARM_VE_SMB_NOR1_SZ                      SIZE_64MB
  46 // SRAM
  47 #define ARM_VE_SMB_SRAM_BASE                    0x48000000
  48 #define ARM_VE_SMB_SRAM_SZ                      SIZE_32MB
  49 // USB, Ethernet, VRAM
  50 #define ARM_VE_SMB_PERIPH_BASE                  0x4C000000
  51 #define PL111_CLCD_VRAM_MOTHERBOARD_BASE        ARM_VE_SMB_PERIPH_BASE
  52 #define ARM_VE_SMB_PERIPH_SZ                    SIZE_64MB
  53
  54 // DRAM
  55 #define ARM_VE_DRAM_BASE                        0x60000000
  56 #define ARM_VE_DRAM_SZ                          0x40000000
  57 // Inside the DRAM we allocate a section for the VRAM (Video RAM)
  58 #define LCD_VRAM_CORE_TILE_BASE                 0x64000000
  59
  60 // External AXI between daughterboards (Logic Tile)
  61 #define ARM_VE_EXT_AXI_BASE                     0xE0000000
  62 #define ARM_VE_EXT_AXI_SZ                       0x20000000  /* 512 MB */
  63
  64
  65 /***********************************************************************************
  66    Core Tile memory-mapped Peripherals
  67 ************************************************************************************/
  68
  69 // PL111 Colour LCD Controller - core tile
  70 #define PL111_CLCD_CORE_TILE_BASE               (ARM_VE_BOARD_PERIPH_BASE + 0x20000)
  71
  72 // PL341 Dynamic Memory Controller Base
  73 #define ARM_VE_DMC_BASE                         (ARM_VE_BOARD_PERIPH_BASE + 0xE0000)
  74
  75 // PL354 Static Memory Controller Base
  76 #define ARM_VE_SMC_CTRL_BASE                    (ARM_VE_BOARD_PERIPH_BASE + 0xE1000)
  77
  78 // System Configuration Controller register Base addresses
  79 //#define ARM_VE_SYS_CFG_CTRL_BASE              (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)
  80 #define ARM_VE_SYS_CFGRW0_REG                   (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)
  81 #define ARM_VE_SYS_CFGRW1_REG                   (ARM_VE_BOARD_PERIPH_BASE + 0xE2004)
  82 #define ARM_VE_SYS_CFGRW2_REG                   (ARM_VE_BOARD_PERIPH_BASE + 0xE2008)
  83
  84 #define ARM_PLATFORM_SCC_BASE                   ARM_VE_SYS_CFGRW0_REG
  85
  86 // SP805 Watchdog on Cortex A9 core tile
  87 #define SP805_WDOG_CORE_TILE_BASE               (ARM_VE_BOARD_PERIPH_BASE + 0xE5000)
  88
  89 // BP147 TZPC Base Address
  90 #define ARM_VE_TZPC_BASE                        (ARM_VE_BOARD_PERIPH_BASE + 0xE6000)
  91
  92 // PL301 Fast AXI Base Address
  93 #define ARM_VE_FAXI_BASE                        (ARM_VE_BOARD_PERIPH_BASE + 0xE9000)
  94
  95 // TZASC Trust Zone Address Space Controller Base Address
  96 #define ARM_VE_TZASC_BASE                       (ARM_VE_BOARD_PERIPH_BASE + 0xEC000)
  97
  98 // PL310 L2x0 Cache Controller Base Address
  99 //#define ARM_VE_L2x0_CTLR_BASE                 0x1E00A000
 100
 101 /***********************************************************************************
 102    Select between Motherboard and Core Tile peripherals
 103 ************************************************************************************/
 104
 105 // Specify which PL111 to use
 106 //#define PL111_CLCD_BASE                       PL111_CLCD_MOTHERBOARD_BASE
 107 #define PL111_CLCD_BASE                         PL111_CLCD_CORE_TILE_BASE
 108
 109 // Specify which Watchdog to use
 110 #define SP805_WDOG_BASE                         SP805_WDOG_MOTHERBOARD_BASE
 111 //#define SP805_WDOG_BASE                       SP805_WDOG_CORE_TILE_BASE
 112
 113 /***********************************************************************************
 114    Peripherals' misc settings
 115 ************************************************************************************/
 116
 117 #define ARM_VE_CFGRW1_TZASC_EN_BIT_MASK         0x2000
 118 #define ARM_VE_CFGRW1_REMAP_NOR0                0
 119 #define ARM_VE_CFGRW1_REMAP_NOR1                (1 << 28)
 120 #define ARM_VE_CFGRW1_REMAP_EXT_AXI             (1 << 29)
 121 #define ARM_VE_CFGRW1_REMAP_DRAM                (1 << 30)
 122
 123 // TZASC - Other settings
 124 #define ARM_VE_DECPROT_BIT_TZPC                 (1 << 6)
 125 #define ARM_VE_DECPROT_BIT_DMC_TZASC            (1 << 11)
 126 #define ARM_VE_DECPROT_BIT_NMC_TZASC            (1 << 12)
 127 #define ARM_VE_DECPROT_BIT_SMC_TZASC            (1 << 13)
 128 #define ARM_VE_DECPROT_BIT_EXT_MAST_TZ          (1)
 129 #define ARM_VE_DECPROT_BIT_DMC_TZASC_LOCK       (1 << 3)
 130 #define ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK       (1 << 4)
 131 #define ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK       (1 << 5)
 132
 133 // PL031 RTC - Other settings
 134 #define PL031_PPM_ACCURACY                      300000000
 135
 136 // SP805 Watchdog - Other settings
 137 #define SP805_CLOCK_FREQUENCY                   32000
 138 #define SP805_MAX_TICKS                         0xFFFFFFFF
 139
 140 // PL111 Lcd
 141 #define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID  1
 142
 143 /***********************************************************************************
 144 // EFI Memory Map in Permanent Memory (DRAM)
 145 ************************************************************************************/
 146
 147 // This region is allocated at the bottom of the DRAM. It will be used
 148 // for fixed address allocations such as Vector Table
 149 #define ARM_VE_EFI_FIX_ADDRESS_REGION_SZ        SIZE_8MB
 150
 151 // This region is the memory declared to PEI as permanent memory for PEI
 152 // and DXE. EFI stacks and heaps will be declared in this region.
 153 #define ARM_VE_EFI_MEMORY_REGION_SZ             SIZE_256MB
 154
 155 #endif