ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2012, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Library/ArmPlatformLib.h>
  16 #include <Library/DebugLib.h>
  17 #include <Library/HobLib.h>
  18 #include <Library/IoLib.h>
  19 #include <Library/MemoryAllocationLib.h>
  20 #include <Library/PcdLib.h>
  21
  22 #include <ArmPlatform.h>
  23
  24 #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 14
  25
  26 // DDR attributes
  27 #define DDR_ATTRIBUTES_CACHED           ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
  28 #define DDR_ATTRIBUTES_UNCACHED         ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
  29
  30 /**
  31   Return the Virtual Memory Map of your platform
  32
  33   This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
  34
  35   @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
  36                                     Virtual Memory mapping. This array must be ended by a zero-filled
  37                                     entry
  38
  39 **/
  40 VOID
  41 ArmPlatformGetVirtualMemoryMap (
  42   IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
  43   )
  44 {
  45   ARM_MEMORY_REGION_ATTRIBUTES  CacheAttributes;
  46   UINTN                         Index = 0;
  47   ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
  48
  49   ASSERT (VirtualMemoryMap != NULL);
  50
  51   VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
  52   if (VirtualMemoryTable == NULL) {
  53     return;
  54   }
  55
  56   if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
  57     CacheAttributes = DDR_ATTRIBUTES_CACHED;
  58   } else {
  59     CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
  60   }
  61
  62   // Detect if it is a 1GB or 2GB Test Chip
  63   //   [16:19]: 0=1GB TC2, 1=2GB TC2
  64   if (MmioRead32(ARM_VE_SYS_PROCID0_REG) & (0xF << 16)) {
  65     DEBUG((EFI_D_ERROR,"Info: 2GB Test Chip 2 detected.\n"));
  66     BuildResourceDescriptorHob (
  67         EFI_RESOURCE_SYSTEM_MEMORY,
  68         EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  69           EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
  70           EFI_RESOURCE_ATTRIBUTE_TESTED,
  71         PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize),
  72         0x40000000
  73     );
  74   }
  75
  76 #ifdef ARM_BIGLITTLE_TC2
  77   // Secure NOR0 Flash
  78   VirtualMemoryTable[Index].PhysicalBase    = ARM_VE_SEC_NOR0_BASE;
  79   VirtualMemoryTable[Index].VirtualBase     = ARM_VE_SEC_NOR0_BASE;
  80   VirtualMemoryTable[Index].Length          = ARM_VE_SEC_NOR0_SZ;
  81   VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
  82   // Secure RAM
  83   VirtualMemoryTable[++Index].PhysicalBase  = ARM_VE_SEC_RAM0_BASE;
  84   VirtualMemoryTable[Index].VirtualBase     = ARM_VE_SEC_RAM0_BASE;
  85   VirtualMemoryTable[Index].Length          = ARM_VE_SEC_RAM0_SZ;
  86   VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
  87 #endif
  88
  89   // SMB CS0 - NOR0 Flash
  90   VirtualMemoryTable[Index].PhysicalBase    = ARM_VE_SMB_NOR0_BASE;
  91   VirtualMemoryTable[Index].VirtualBase     = ARM_VE_SMB_NOR0_BASE;
  92   VirtualMemoryTable[Index].Length          = SIZE_256KB * 255;
  93   VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
  94   // Environment Variables region
  95   VirtualMemoryTable[++Index].PhysicalBase  = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
  96   VirtualMemoryTable[Index].VirtualBase     = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
  97   VirtualMemoryTable[Index].Length          = SIZE_64KB * 4;
  98   VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
  99
 100   // SMB CS1 or CS4 - NOR1 Flash
 101   VirtualMemoryTable[++Index].PhysicalBase  = ARM_VE_SMB_NOR1_BASE;
 102   VirtualMemoryTable[Index].VirtualBase     = ARM_VE_SMB_NOR1_BASE;
 103   VirtualMemoryTable[Index].Length          = SIZE_256KB * 255;
 104   VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 105   // Environment Variables region
 106   VirtualMemoryTable[++Index].PhysicalBase  = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255);
 107   VirtualMemoryTable[Index].VirtualBase     = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255);
 108   VirtualMemoryTable[Index].Length          = SIZE_64KB * 4;
 109   VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 110
 111   // SMB CS3 or CS1 - PSRAM
 112   VirtualMemoryTable[++Index].PhysicalBase  = ARM_VE_SMB_SRAM_BASE;
 113   VirtualMemoryTable[Index].VirtualBase     = ARM_VE_SMB_SRAM_BASE;
 114   VirtualMemoryTable[Index].Length          = ARM_VE_SMB_SRAM_SZ;
 115   VirtualMemoryTable[Index].Attributes      = CacheAttributes;
 116
 117   // Motherboard peripherals
 118   VirtualMemoryTable[++Index].PhysicalBase  = ARM_VE_SMB_PERIPH_BASE;
 119   VirtualMemoryTable[Index].VirtualBase     = ARM_VE_SMB_PERIPH_BASE;
 120   VirtualMemoryTable[Index].Length          = ARM_VE_SMB_PERIPH_SZ;
 121   VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 122
 123 #ifdef ARM_BIGLITTLE_TC2
 124   // Non-secure ROM
 125   VirtualMemoryTable[++Index].PhysicalBase  = ARM_VE_TC2_NON_SECURE_ROM_BASE;
 126   VirtualMemoryTable[Index].VirtualBase     = ARM_VE_TC2_NON_SECURE_ROM_BASE;
 127   VirtualMemoryTable[Index].Length          = ARM_VE_TC2_NON_SECURE_ROM_SZ;
 128   VirtualMemoryTable[Index].Attributes      = CacheAttributes;
 129 #endif
 130
 131   // OnChip peripherals
 132   VirtualMemoryTable[++Index].PhysicalBase  = ARM_VE_ONCHIP_PERIPH_BASE;
 133   VirtualMemoryTable[Index].VirtualBase     = ARM_VE_ONCHIP_PERIPH_BASE;
 134   VirtualMemoryTable[Index].Length          = ARM_VE_ONCHIP_PERIPH_SZ;
 135   VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 136
 137   // SCC Region
 138   VirtualMemoryTable[++Index].PhysicalBase  = ARM_CTA15A7_SCC_BASE;
 139   VirtualMemoryTable[Index].VirtualBase     = ARM_CTA15A7_SCC_BASE;
 140   VirtualMemoryTable[Index].Length          = SIZE_64KB;
 141   VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 142
 143 #ifdef ARM_BIGLITTLE_TC2
 144   // TC2 OnChip non-secure SRAM
 145   VirtualMemoryTable[++Index].PhysicalBase  = ARM_VE_TC2_NON_SECURE_SRAM_BASE;
 146   VirtualMemoryTable[Index].VirtualBase     = ARM_VE_TC2_NON_SECURE_SRAM_BASE;
 147   VirtualMemoryTable[Index].Length          = ARM_VE_TC2_NON_SECURE_SRAM_SZ;
 148   VirtualMemoryTable[Index].Attributes      = CacheAttributes;
 149 #endif
 150
 151 #ifndef ARM_BIGLITTLE_TC2
 152   // Workaround for SRAM bug in RTSM
 153   if (PcdGet32 (PcdSystemMemoryBase) != 0x80000000) {
 154     VirtualMemoryTable[++Index].PhysicalBase  = 0x80000000;
 155     VirtualMemoryTable[Index].VirtualBase     = 0x80000000;
 156     VirtualMemoryTable[Index].Length          = PcdGet32 (PcdSystemMemoryBase) - 0x80000000;
 157     VirtualMemoryTable[Index].Attributes      = CacheAttributes;
 158   }
 159 #endif
 160
 161   // DDR
 162   VirtualMemoryTable[++Index].PhysicalBase  = PcdGet32 (PcdSystemMemoryBase);
 163   VirtualMemoryTable[Index].VirtualBase     = PcdGet32 (PcdSystemMemoryBase);
 164   VirtualMemoryTable[Index].Length          = PcdGet32 (PcdSystemMemorySize);
 165   VirtualMemoryTable[Index].Attributes      = CacheAttributes;
 166
 167   // End of Table
 168   VirtualMemoryTable[++Index].PhysicalBase  = 0;
 169   VirtualMemoryTable[Index].VirtualBase     = 0;
 170   VirtualMemoryTable[Index].Length          = 0;
 171   VirtualMemoryTable[Index].Attributes      = (ARM_MEMORY_REGION_ATTRIBUTES)0;
 172
 173   ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
 174
 175   *VirtualMemoryMap = VirtualMemoryTable;
 176 }
 177
 178 /**
 179   Return the EFI Memory Map provided by extension memory on your platform
 180
 181   This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource
 182   Descriptor HOBs used by DXE core.
 183
 184   @param[out]   EfiMemoryMap        Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an
 185                                     EFI Memory region. This array must be ended by a zero-filled entry
 186
 187 **/
 188 EFI_STATUS
 189 ArmPlatformGetAdditionalSystemMemory (
 190   OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap
 191   )
 192 {
 193   return EFI_UNSUPPORTED;
 194 }