ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Library/IoLib.h>
  16 #include <Library/ArmTrustZoneLib.h>
  17 #include <Library/ArmPlatformLib.h>
  18 #include <Library/DebugLib.h>
  19 #include <Library/PcdLib.h>
  20 #include <Library/SerialPortLib.h>
  21
  22 #include <Drivers/PL341Dmc.h>
  23 #include <Drivers/PL301Axi.h>
  24 #include <Drivers/SP804Timer.h>
  25
  26 #include <ArmPlatform.h>
  27
  28 #define SerialPrint(txt)  SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1);
  29
  30 // DDR2 timings
  31 PL341_DMC_CONFIG DDRTimings = {
  32   .base   = ARM_VE_DMC_BASE,
  33   .phy_ctrl_base  = 0x0,  //There is no DDR2 PHY controller on CTA9 test chip
  34   .MaxChip   = 1,
  35   .IsUserCfg = TRUE,
  36   .User0Cfg = 0x7C924924,
  37   .User2Cfg = (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) | (0x1 << TC_UIOHOCT_SHIFT) | (0x1 << TC_UIOHSTOP_SHIFT),
  38   .HasQos    = TRUE,
  39   .refresh_prd  = 0x3D0,
  40   .cas_latency  = 0x8,
  41   .write_latency  = 0x3,
  42   .t_mrd    = 0x2,
  43   .t_ras    = 0xA,
  44   .t_rc   = 0xE,
  45   .t_rcd    = 0x104,
  46   .t_rfc    = 0x2f32,
  47   .t_rp   = 0x14,
  48   .t_rrd    = 0x2,
  49   .t_wr   = 0x4,
  50   .t_wtr    = 0x2,
  51   .t_xp   = 0x2,
  52   .t_xsr    = 0xC8,
  53   .t_esr    = 0x14,
  54   .MemoryCfg   = DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 | DMC_MEMORY_CONFIG_BURST_4 |
  55                         DMC_MEMORY_CONFIG_ROW_ADDRESS_15 | DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10,
  56   .MemoryCfg2  = DMC_MEMORY_CFG2_DQM_INIT | DMC_MEMORY_CFG2_CKE_INIT |
  57             DMC_MEMORY_CFG2_BANK_BITS_3 | DMC_MEMORY_CFG2_MEM_WIDTH_32,
  58   .MemoryCfg3  = 0x00000001,
  59   .ChipCfg0    = 0x00010000,
  60   .t_faw    = 0x00000A0D,
  61   .ModeReg = DDR2_MR_BURST_LENGTH_4 | DDR2_MR_CAS_LATENCY_4 | DDR2_MR_WR_CYCLES_4,
  62   .ExtModeReg = DDR_EMR_RTT_50R | (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK),
  63 };
  64
  65 /**
  66   Return if Trustzone is supported by your platform
  67
  68   A non-zero value must be returned if you want to support a Secure World on your platform.
  69   ArmVExpressTrustzoneInit() will later set up the secure regions.
  70   This function can return 0 even if Trustzone is supported by your processor. In this case,
  71   the platform will continue to run in Secure World.
  72
  73   @return   A non-zero value if Trustzone supported.
  74
  75 **/
  76 UINTN
  77 ArmPlatformTrustzoneSupported (
  78   VOID
  79   )
  80 {
  81   return (MmioRead32(ARM_VE_SYS_CFGRW1_REG) & ARM_VE_CFGRW1_TZASC_EN_BIT_MASK);
  82 }
  83
  84 /**
  85   Return the current Boot Mode
  86
  87   This function returns the boot reason on the platform
  88
  89   @return   Return the current Boot Mode of the platform
  90
  91 **/
  92 EFI_BOOT_MODE
  93 ArmPlatformGetBootMode (
  94   VOID
  95   )
  96 {
  97   return BOOT_WITH_FULL_CONFIGURATION;
  98 }
  99
 100 /**
 101   Remap the memory at 0x0
 102
 103   Some platform requires or gives the ability to remap the memory at the address 0x0.
 104   This function can do nothing if this feature is not relevant to your platform.
 105
 106 **/
 107 VOID
 108 ArmPlatformBootRemapping (
 109   VOID
 110   )
 111 {
 112   UINT32 Value;
 113
 114   if (FeaturePcdGet(PcdNorFlashRemapping)) {
 115     SerialPrint ("Secure ROM at 0x0\n\r");
 116   } else {
 117     Value = MmioRead32(ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1
 118     // Remap the DRAM to 0x0
 119     MmioWrite32(ARM_VE_SYS_CFGRW1_REG, (Value & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM);
 120   }
 121 }
 122
 123 /**
 124   Initialize controllers that must setup in the normal world
 125
 126   This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
 127   in the PEI phase.
 128
 129 **/
 130 VOID
 131 ArmPlatformNormalInitialize (
 132   VOID
 133   )
 134 {
 135   // Configure periodic timer (TIMER0) for 1MHz operation
 136   MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
 137   // Configure 1MHz clock
 138   MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
 139   // configure SP810 to use 1MHz clock and disable
 140   MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
 141   // Configure SP810 to use 1MHz clock and disable
 142   MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
 143 }
 144
 145 /**
 146   Initialize the system (or sometimes called permanent) memory
 147
 148   This memory is generally represented by the DRAM.
 149
 150 **/
 151 VOID
 152 ArmPlatformInitializeSystemMemory (
 153   VOID
 154   )
 155 {
 156   PL341DmcInit(&DDRTimings);
 157   PL301AxiInit(ARM_VE_FAXI_BASE);
 158 }