ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/Arm/RTSMHelper.S

   1 #
   2 #  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
   3 #
   4 #  This program and the accompanying materials
   5 #  are licensed and made available under the terms and conditions of the BSD License
   6 #  which accompanies this distribution.  The full text of the license may be found at
   7 #  http://opensource.org/licenses/bsd-license.php
   8 #
   9 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 #
  12 #
  13
  14 #include <AsmMacroIoLib.h>
  15 #include <Base.h>
  16 #include <Library/ArmLib.h>
  17 #include <Library/PcdLib.h>
  18 #include <AutoGen.h>
  19 #include "AsmMacroIoLib.inc"
  20
  21 #include <Chipset/ArmCortexA9.h>
  22
  23 .text
  24 .align 2
  25
  26 GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
  27 GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)
  28 GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
  29 GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
  30 GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
  31
  32 GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)
  33 GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)
  34
  35 ASM_PFX(ArmPlatformPeiBootAction):
  36   bx    lr
  37
  38 # IN None
  39 # OUT r0 = SCU Base Address
  40 ASM_PFX(ArmGetScuBaseAddress):
  41   # Read Configuration Base Address Register. ArmCBar cannot be called to get
  42   # the Configuration BAR as a stack is not necessary setup. The SCU is at the
  43   # offset 0x0000 from the Private Memory Region.
  44   mrc   p15, 4, r0, c15, c0, 0
  45   bx    lr
  46
  47 //UINTN
  48 //ArmPlatformGetPrimaryCoreMpId (
  49 //  VOID
  50 //  );
  51 ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
  52   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)
  53   ldr   r0, [r0]
  54   bx    lr
  55
  56 # IN None
  57 # OUT r0 = number of cores present in the system
  58 ASM_PFX(ArmGetCpuCountPerCluster):
  59   stmfd SP!, {r1-r2}
  60
  61   # Read CP15 MIDR
  62   mrc   p15, 0, r1, c0, c0, 0
  63
  64   # Check if the CPU is A15
  65   mov   r1, r1, LSR #4
  66   LoadConstantToReg (ARM_CPU_TYPE_MASK, r0)
  67   and   r1, r1, r0
  68
  69   LoadConstantToReg (ARM_CPU_TYPE_A15, r0)
  70   cmp   r1, r0
  71   beq   _Read_cp15_reg
  72
  73 _CPU_is_not_A15:
  74   mov   r2, lr                           @ Save link register
  75   bl    ArmGetScuBaseAddress             @ Read SCU Base Address
  76   mov   lr, r2                           @ Restore link register val
  77   ldr   r0, [r0, #A9_SCU_CONFIG_OFFSET]     @ Read SCU Config reg to get CPU count
  78   b     _Return
  79
  80 _Read_cp15_reg:
  81   mrc   p15, 1, r0, c9, c0, 2            @ Read C9 register of CP15 to get CPU count
  82   lsr   r0, #24
  83
  84 _Return:
  85   and   r0, r0, #3
  86   # Add '1' to the number of CPU on the Cluster
  87   add   r0, r0, #1
  88   ldmfd SP!, {r1-r2}
  89   bx lr
  90
  91 //UINTN
  92 //ArmPlatformIsPrimaryCore (
  93 //  IN UINTN MpId
  94 //  );
  95 ASM_PFX(ArmPlatformIsPrimaryCore):
  96   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)
  97   ldr   r1, [r1]
  98   and   r0, r0, r1
  99   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)
 100   ldr   r1, [r1]
 101   cmp   r0, r1
 102   moveq r0, #1
 103   movne r0, #0
 104   bx    lr
 105
 106 //UINTN
 107 //ArmPlatformGetCorePosition (
 108 //  IN UINTN MpId
 109 //  );
 110 ASM_PFX(ArmPlatformGetCorePosition):
 111   and   r1, r0, #ARM_CORE_MASK
 112   and   r0, r0, #ARM_CLUSTER_MASK
 113   add   r0, r1, r0, LSR #7
 114   bx    lr
 115
 116 ASM_FUNCTION_REMOVE_IF_UNREFERENCED