ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/Arm/RTSMHelper.S

   1 #
   2 #  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
   3 #
   4 #  This program and the accompanying materials
   5 #  are licensed and made available under the terms and conditions of the BSD License
   6 #  which accompanies this distribution.  The full text of the license may be found at
   7 #  http://opensource.org/licenses/bsd-license.php
   8 #
   9 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 #
  12 #
  13
  14 #include <AsmMacroIoLib.h>
  15 #include <Base.h>
  16 #include <Library/ArmLib.h>
  17 #include <Library/PcdLib.h>
  18 #include <AutoGen.h>
  19
  20 #include <Chipset/ArmCortexA9.h>
  21
  22 .text
  23 .align 2
  24
  25 GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)
  26 GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
  27 GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
  28 GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
  29
  30 GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)
  31 GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)
  32
  33 # IN None
  34 # OUT r0 = SCU Base Address
  35 ASM_PFX(ArmGetScuBaseAddress):
  36   # Read Configuration Base Address Register. ArmCBar cannot be called to get
  37   # the Configuration BAR as a stack is not necessary setup. The SCU is at the
  38   # offset 0x0000 from the Private Memory Region.
  39   mrc   p15, 4, r0, c15, c0, 0
  40   bx  lr
  41
  42 //UINTN
  43 //ArmPlatformGetPrimaryCoreMpId (
  44 //  VOID
  45 //  );
  46 ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
  47   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r0)
  48   ldr   r0, [r0]
  49   bx    lr
  50
  51 # IN None
  52 # OUT r0 = number of cores present in the system
  53 ASM_PFX(ArmGetCpuCountPerCluster):
  54   stmfd SP!, {r1-r2}
  55
  56   # Read CP15 MIDR
  57   mrc   p15, 0, r1, c0, c0, 0
  58
  59   # Check if the CPU is A15
  60   mov   r1, r1, LSR #4
  61   LoadConstantToReg (ARM_CPU_TYPE_MASK, r0)
  62   and   r1, r1, r0
  63
  64   LoadConstantToReg (ARM_CPU_TYPE_A15, r0)
  65   cmp   r1, r0
  66   beq   _Read_cp15_reg
  67
  68 _CPU_is_not_A15:
  69   mov   r2, lr                           @ Save link register
  70   bl    ArmGetScuBaseAddress             @ Read SCU Base Address
  71   mov   lr, r2                           @ Restore link register val
  72   ldr   r0, [r0, #A9_SCU_CONFIG_OFFSET]     @ Read SCU Config reg to get CPU count
  73   b     _Return
  74
  75 _Read_cp15_reg:
  76   mrc   p15, 1, r0, c9, c0, 2            @ Read C9 register of CP15 to get CPU count
  77   lsr   r0, #24
  78
  79 _Return:
  80   and   r0, r0, #3
  81   # Add '1' to the number of CPU on the Cluster
  82   add   r0, r0, #1
  83   ldmfd SP!, {r1-r2}
  84   bx lr
  85
  86 //UINTN
  87 //ArmPlatformIsPrimaryCore (
  88 //  IN UINTN MpId
  89 //  );
  90 ASM_PFX(ArmPlatformIsPrimaryCore):
  91   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)
  92   ldr   r1, [r1]
  93   and   r0, r0, r1
  94   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)
  95   ldr   r1, [r1]
  96   cmp   r0, r1
  97   moveq r0, #1
  98   movne r0, #0
  99   bx    lr
 100
 101 //UINTN
 102 //ArmPlatformGetCorePosition (
 103 //  IN UINTN MpId
 104 //  );
 105 ASM_PFX(ArmPlatformGetCorePosition):
 106   and   r1, r0, #ARM_CORE_MASK
 107   and   r0, r0, #ARM_CLUSTER_MASK
 108   add   r0, r1, r0, LSR #7
 109   bx    lr
 110
 111 ASM_FUNCTION_REMOVE_IF_UNREFERENCED