ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/Arm/RTSMHelper.S

   1 #
   2 #  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
   3 #
   4 #  This program and the accompanying materials
   5 #  are licensed and made available under the terms and conditions of the BSD License
   6 #  which accompanies this distribution.  The full text of the license may be found at
   7 #  http://opensource.org/licenses/bsd-license.php
   8 #
   9 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 #
  12 #
  13
  14 #include <AsmMacroIoLib.h>
  15 #include <Base.h>
  16 #include <Library/PcdLib.h>
  17 #include <AutoGen.h>
  18
  19 #include <Chipset/ArmCortexA9.h>
  20
  21 .text
  22 .align 2
  23
  24 GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)
  25 GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
  26
  27 GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)
  28 GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)
  29
  30 # IN None
  31 # OUT r0 = SCU Base Address
  32 ASM_PFX(ArmGetScuBaseAddress):
  33   # Read Configuration Base Address Register. ArmCBar cannot be called to get
  34   # the Configuration BAR as a stack is not necessary setup. The SCU is at the
  35   # offset 0x0000 from the Private Memory Region.
  36   mrc   p15, 4, r0, c15, c0, 0
  37   bx  lr
  38
  39 # IN None
  40 # OUT r0 = number of cores present in the system
  41 ASM_PFX(ArmGetCpuCountPerCluster):
  42   stmfd SP!, {r1-r2}
  43
  44   # Read CP15 MIDR
  45   mrc   p15, 0, r1, c0, c0, 0
  46
  47   # Check if the CPU is A15
  48   mov   r1, r1, LSR #4
  49   LoadConstantToReg (ARM_CPU_TYPE_MASK, r0)
  50   and   r1, r1, r0
  51
  52   LoadConstantToReg (ARM_CPU_TYPE_A15, r0)
  53   cmp   r1, r0
  54   beq   _Read_cp15_reg
  55
  56 _CPU_is_not_A15:
  57   mov   r2, lr                           @ Save link register
  58   bl    ArmGetScuBaseAddress             @ Read SCU Base Address
  59   mov   lr, r2                           @ Restore link register val
  60   ldr   r0, [r0, #A9_SCU_CONFIG_OFFSET]     @ Read SCU Config reg to get CPU count
  61   b     _Return
  62
  63 _Read_cp15_reg:
  64   mrc   p15, 1, r0, c9, c0, 2            @ Read C9 register of CP15 to get CPU count
  65   lsr   r0, #24
  66
  67 _Return:
  68   and   r0, r0, #3
  69   # Add '1' to the number of CPU on the Cluster
  70   add   r0, r0, #1
  71   ldmfd SP!, {r1-r2}
  72   bx lr
  73
  74 //UINTN
  75 //ArmPlatformIsPrimaryCore (
  76 //  IN UINTN MpId
  77 //  );
  78 ASM_PFX(ArmPlatformIsPrimaryCore):
  79   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)
  80   ldr   r1, [r1]
  81   and   r0, r0, r1
  82   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)
  83   ldr   r1, [r1]
  84   cmp   r0, r1
  85   moveq r0, #1
  86   movne r0, #0
  87   bx    lr
  88
  89 ASM_FUNCTION_REMOVE_IF_UNREFERENCED