ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/Arm/RTSMHelper.S

   1 #
   2 #  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
   3 #
   4 #  This program and the accompanying materials
   5 #  are licensed and made available under the terms and conditions of the BSD License
   6 #  which accompanies this distribution.  The full text of the license may be found at
   7 #  http://opensource.org/licenses/bsd-license.php
   8 #
   9 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 #
  12 #
  13
  14 #include <AsmMacroIoLib.h>
  15 #include <Base.h>
  16 #include <Library/PcdLib.h>
  17 #include <AutoGen.h>
  18
  19 #include <Chipset/ArmCortexA9.h>
  20
  21 .text
  22 .align 2
  23
  24 GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)
  25 GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
  26 GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
  27
  28 GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)
  29 GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)
  30
  31 # IN None
  32 # OUT r0 = SCU Base Address
  33 ASM_PFX(ArmGetScuBaseAddress):
  34   # Read Configuration Base Address Register. ArmCBar cannot be called to get
  35   # the Configuration BAR as a stack is not necessary setup. The SCU is at the
  36   # offset 0x0000 from the Private Memory Region.
  37   mrc   p15, 4, r0, c15, c0, 0
  38   bx  lr
  39
  40 //UINTN
  41 //ArmPlatformGetPrimaryCoreMpId (
  42 //  VOID
  43 //  );
  44 ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
  45   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r0)
  46   ldr   r0, [r0]
  47   bx    lr
  48
  49 # IN None
  50 # OUT r0 = number of cores present in the system
  51 ASM_PFX(ArmGetCpuCountPerCluster):
  52   stmfd SP!, {r1-r2}
  53
  54   # Read CP15 MIDR
  55   mrc   p15, 0, r1, c0, c0, 0
  56
  57   # Check if the CPU is A15
  58   mov   r1, r1, LSR #4
  59   LoadConstantToReg (ARM_CPU_TYPE_MASK, r0)
  60   and   r1, r1, r0
  61
  62   LoadConstantToReg (ARM_CPU_TYPE_A15, r0)
  63   cmp   r1, r0
  64   beq   _Read_cp15_reg
  65
  66 _CPU_is_not_A15:
  67   mov   r2, lr                           @ Save link register
  68   bl    ArmGetScuBaseAddress             @ Read SCU Base Address
  69   mov   lr, r2                           @ Restore link register val
  70   ldr   r0, [r0, #A9_SCU_CONFIG_OFFSET]     @ Read SCU Config reg to get CPU count
  71   b     _Return
  72
  73 _Read_cp15_reg:
  74   mrc   p15, 1, r0, c9, c0, 2            @ Read C9 register of CP15 to get CPU count
  75   lsr   r0, #24
  76
  77 _Return:
  78   and   r0, r0, #3
  79   # Add '1' to the number of CPU on the Cluster
  80   add   r0, r0, #1
  81   ldmfd SP!, {r1-r2}
  82   bx lr
  83
  84 //UINTN
  85 //ArmPlatformIsPrimaryCore (
  86 //  IN UINTN MpId
  87 //  );
  88 ASM_PFX(ArmPlatformIsPrimaryCore):
  89   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)
  90   ldr   r1, [r1]
  91   and   r0, r0, r1
  92   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)
  93   ldr   r1, [r1]
  94   cmp   r0, r1
  95   moveq r0, #1
  96   movne r0, #0
  97   bx    lr
  98
  99 ASM_FUNCTION_REMOVE_IF_UNREFERENCED