ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/Arm/RTSMHelper.asm

   1 //
   2 //  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
   3 //
   4 //  This program and the accompanying materials
   5 //  are licensed and made available under the terms and conditions of the BSD License
   6 //  which accompanies this distribution.  The full text of the license may be found at
   7 //  http://opensource.org/licenses/bsd-license.php
   8 //
   9 //  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 //  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 //
  12 //
  13
  14 #include <AsmMacroIoLib.h>
  15 #include <Base.h>
  16 #include <Library/ArmLib.h>
  17 #include <Library/PcdLib.h>
  18
  19 #include <Chipset/ArmCortexA9.h>
  20
  21 #include <AutoGen.h>
  22
  23   INCLUDE AsmMacroIoLib.inc
  24
  25   EXPORT    ArmGetCpuCountPerCluster
  26   EXPORT    ArmPlatformIsPrimaryCore
  27   EXPORT    ArmPlatformGetPrimaryCoreMpId
  28   EXPORT    ArmPlatformGetCorePosition
  29
  30   IMPORT    _gPcd_FixedAtBuild_PcdArmPrimaryCore
  31   IMPORT    _gPcd_FixedAtBuild_PcdArmPrimaryCoreMask
  32
  33   AREA RTSMHelper, CODE, READONLY
  34
  35 // IN None
  36 // OUT r0 = SCU Base Address
  37 ArmGetScuBaseAddress FUNCTION
  38   // Read Configuration Base Address Register. ArmCBar cannot be called to get
  39   // the Configuration BAR as a stack is not necessary setup. The SCU is at the
  40   // offset 0x0000 from the Private Memory Region.
  41   mrc   p15, 4, r0, c15, c0, 0
  42   bx  lr
  43   ENDFUNC
  44
  45 //UINTN
  46 //ArmPlatformGetPrimaryCoreMpId (
  47 //  VOID
  48 //  );
  49 ArmPlatformGetPrimaryCoreMpId FUNCTION
  50   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r0)
  51   ldr   r0, [r0]
  52   bx    lr
  53   ENDFUNC
  54
  55 // IN None
  56 // OUT r0 = number of cores present in the system
  57 ArmGetCpuCountPerCluster FUNCTION
  58   stmfd SP!, {r1-r2}
  59
  60   // Read CP15 MIDR
  61   mrc   p15, 0, r1, c0, c0, 0
  62
  63   // Check if the CPU is A15
  64   mov   r1, r1, LSR #4
  65   mov   r0, #ARM_CPU_TYPE_MASK
  66   and   r1, r1, r0
  67
  68   mov   r0, #ARM_CPU_TYPE_A15
  69   cmp   r1, r0
  70   beq   _Read_cp15_reg
  71
  72 _CPU_is_not_A15
  73   mov   r2, lr                              ; Save link register
  74   bl    ArmGetScuBaseAddress                ; Read SCU Base Address
  75   mov   lr, r2                              ; Restore link register val
  76   ldr   r0, [r0, #A9_SCU_CONFIG_OFFSET]     ; Read SCU Config reg to get CPU count
  77   b     _Return
  78
  79 _Read_cp15_reg
  80   mrc   p15, 1, r0, c9, c0, 2            ; Read C9 register of CP15 to get CPU count
  81   lsr   r0, #24
  82
  83
  84 _Return
  85   and   r0, r0, #3
  86   // Add '1' to the number of CPU on the Cluster
  87   add   r0, r0, #1
  88   ldmfd SP!, {r1-r2}
  89   bx lr
  90   ENDFUNC
  91
  92 //UINTN
  93 //ArmPlatformIsPrimaryCore (
  94 //  IN UINTN MpId
  95 //  );
  96 ArmPlatformIsPrimaryCore FUNCTION
  97   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)
  98   ldr   r1, [r1]
  99   and   r0, r0, r1
 100   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)
 101   ldr   r1, [r1]
 102   cmp   r0, r1
 103   moveq r0, #1
 104   movne r0, #0
 105   bx    lr
 106   ENDFUNC
 107
 108 //UINTN
 109 //ArmPlatformGetCorePosition (
 110 //  IN UINTN MpId
 111 //  );
 112 ArmPlatformGetCorePosition FUNCTION
 113   and   r1, r0, #ARM_CORE_MASK
 114   and   r0, r0, #ARM_CLUSTER_MASK
 115   add   r0, r1, r0, LSR #7
 116   bx    lr
 117   ENDFUNC
 118
 119   END