ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/Arm/RTSMHelper.asm

   1 //
   2 //  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
   3 //
   4 //  This program and the accompanying materials
   5 //  are licensed and made available under the terms and conditions of the BSD License
   6 //  which accompanies this distribution.  The full text of the license may be found at
   7 //  http://opensource.org/licenses/bsd-license.php
   8 //
   9 //  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 //  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 //
  12 //
  13
  14 #include <AsmMacroIoLib.h>
  15 #include <Base.h>
  16 #include <Library/PcdLib.h>
  17
  18 #include <Chipset/ArmCortexA9.h>
  19
  20 #include <AutoGen.h>
  21
  22   INCLUDE AsmMacroIoLib.inc
  23
  24   EXPORT    ArmGetCpuCountPerCluster
  25   EXPORT    ArmPlatformIsPrimaryCore
  26   EXPORT    ArmPlatformGetPrimaryCoreMpId
  27
  28   IMPORT  _gPcd_FixedAtBuild_PcdArmPrimaryCore
  29   IMPORT  _gPcd_FixedAtBuild_PcdArmPrimaryCoreMask
  30
  31   AREA RTSMHelper, CODE, READONLY
  32
  33 // IN None
  34 // OUT r0 = SCU Base Address
  35 ArmGetScuBaseAddress FUNCTION
  36   // Read Configuration Base Address Register. ArmCBar cannot be called to get
  37   // the Configuration BAR as a stack is not necessary setup. The SCU is at the
  38   // offset 0x0000 from the Private Memory Region.
  39   mrc   p15, 4, r0, c15, c0, 0
  40   bx  lr
  41   ENDFUNC
  42
  43 //UINTN
  44 //ArmPlatformGetPrimaryCoreMpId (
  45 //  VOID
  46 //  );
  47 ArmPlatformGetPrimaryCoreMpId FUNCTION
  48   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r0)
  49   ldr   r0, [r0]
  50   bx    lr
  51   ENDFUNC
  52
  53 // IN None
  54 // OUT r0 = number of cores present in the system
  55 ArmGetCpuCountPerCluster FUNCTION
  56   stmfd SP!, {r1-r2}
  57
  58   // Read CP15 MIDR
  59   mrc   p15, 0, r1, c0, c0, 0
  60
  61   // Check if the CPU is A15
  62   mov   r1, r1, LSR #4
  63   mov   r0, #ARM_CPU_TYPE_MASK
  64   and   r1, r1, r0
  65
  66   mov   r0, #ARM_CPU_TYPE_A15
  67   cmp   r1, r0
  68   beq   _Read_cp15_reg
  69
  70 _CPU_is_not_A15
  71   mov   r2, lr                              ; Save link register
  72   bl    ArmGetScuBaseAddress                ; Read SCU Base Address
  73   mov   lr, r2                              ; Restore link register val
  74   ldr   r0, [r0, #A9_SCU_CONFIG_OFFSET]     ; Read SCU Config reg to get CPU count
  75   b     _Return
  76
  77 _Read_cp15_reg
  78   mrc   p15, 1, r0, c9, c0, 2            ; Read C9 register of CP15 to get CPU count
  79   lsr   r0, #24
  80
  81
  82 _Return
  83   and   r0, r0, #3
  84   // Add '1' to the number of CPU on the Cluster
  85   add   r0, r0, #1
  86   ldmfd SP!, {r1-r2}
  87   bx lr
  88   ENDFUNC
  89
  90 //UINTN
  91 //ArmPlatformIsPrimaryCore (
  92 //  IN UINTN MpId
  93 //  );
  94 ArmPlatformIsPrimaryCore FUNCTION
  95   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)
  96   ldr   r1, [r1]
  97   and   r0, r0, r1
  98   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)
  99   ldr   r1, [r1]
 100   cmp   r0, r1
 101   moveq r0, #1
 102   movne r0, #0
 103   bx    lr
 104   ENDFUNC
 105
 106   END