ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Library/IoLib.h>
  16 #include <Library/ArmPlatformLib.h>
  17 #include <Library/DebugLib.h>
  18 #include <Library/PcdLib.h>
  19
  20 #include <Drivers/SP804Timer.h>
  21
  22 #include <Ppi/ArmMpCoreInfo.h>
  23
  24 #include <ArmPlatform.h>
  25
  26 UINTN
  27 ArmGetCpuCountPerCluster (
  28   VOID
  29   );
  30
  31 ARM_CORE_INFO mVersatileExpressMpCoreInfoTable[] = {
  32   {
  33     // Cluster 0, Core 0
  34     0x0, 0x0,
  35
  36     // MP Core MailBox Set/Get/Clear Addresses and Clear Value
  37     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
  38     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
  39     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
  40     (UINT64)0xFFFFFFFF
  41   },
  42   {
  43     // Cluster 0, Core 1
  44     0x0, 0x1,
  45
  46     // MP Core MailBox Set/Get/Clear Addresses and Clear Value
  47     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
  48     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
  49     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
  50     (UINT64)0xFFFFFFFF
  51   },
  52   {
  53     // Cluster 0, Core 2
  54     0x0, 0x2,
  55
  56     // MP Core MailBox Set/Get/Clear Addresses and Clear Value
  57     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
  58     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
  59     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
  60     (UINT64)0xFFFFFFFF
  61   },
  62   {
  63     // Cluster 0, Core 3
  64     0x0, 0x3,
  65
  66     // MP Core MailBox Set/Get/Clear Addresses and Clear Value
  67     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
  68     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
  69     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
  70     (UINT64)0xFFFFFFFF
  71   }
  72 };
  73
  74 /**
  75   Return the current Boot Mode
  76
  77   This function returns the boot reason on the platform
  78
  79   @return   Return the current Boot Mode of the platform
  80
  81 **/
  82 EFI_BOOT_MODE
  83 ArmPlatformGetBootMode (
  84   VOID
  85   )
  86 {
  87   return BOOT_WITH_FULL_CONFIGURATION;
  88 }
  89
  90 /**
  91   Initialize controllers that must setup in the normal world
  92
  93   This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
  94   in the PEI phase.
  95
  96 **/
  97 VOID
  98 ArmPlatformNormalInitialize (
  99   VOID
 100   )
 101 {
 102   // Disable memory remapping and return to normal mapping
 103   MmioOr32 (SP810_CTRL_BASE, BIT8);
 104 }
 105
 106 /**
 107   Initialize the system (or sometimes called permanent) memory
 108
 109   This memory is generally represented by the DRAM.
 110
 111 **/
 112 VOID
 113 ArmPlatformInitializeSystemMemory (
 114   VOID
 115   )
 116 {
 117   // Configure periodic timer (TIMER0) for 1MHz operation
 118   MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
 119   // Configure 1MHz clock
 120   MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
 121   // configure SP810 to use 1MHz clock and disable
 122   MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
 123   // Configure SP810 to use 1MHz clock and disable
 124   MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
 125 }
 126
 127 EFI_STATUS
 128 PrePeiCoreGetMpCoreInfo (
 129   OUT UINTN                   *CoreCount,
 130   OUT ARM_CORE_INFO           **ArmCoreTable
 131   )
 132 {
 133   UINT32   ProcType;
 134
 135   ProcType = MmioRead32 (ARM_VE_SYS_PROCID0_REG) & ARM_VE_SYS_PROC_ID_MASK;
 136   if ((ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A9) || (ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A15)) {
 137     // Only support one cluster
 138     *CoreCount    = ArmGetCpuCountPerCluster ();
 139     *ArmCoreTable = mVersatileExpressMpCoreInfoTable;
 140     return EFI_SUCCESS;
 141   } else {
 142     return EFI_UNSUPPORTED;
 143   }
 144 }
 145
 146 // Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
 147 EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
 148 ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
 149
 150 EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
 151   {
 152     EFI_PEI_PPI_DESCRIPTOR_PPI,
 153     &mArmMpCoreInfoPpiGuid,
 154     &mMpCoreInfoPpi
 155   }
 156 };
 157
 158 VOID
 159 ArmPlatformGetPlatformPpiList (
 160   OUT UINTN                   *PpiListSize,
 161   OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
 162   )
 163 {
 164   *PpiListSize = sizeof(gPlatformPpiTable);
 165   *PpiList = gPlatformPpiTable;
 166 }