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1 /** @file
2 *
3 * Copyright (c) 2011-2013, ARM Limited. All rights reserved.
4 *
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
9 *
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 *
13 **/
14
15 #include <Library/ArmPlatformLib.h>
16 #include <Library/DebugLib.h>
17 #include <Library/PcdLib.h>
18 #include <Library/IoLib.h>
19 #include <Library/MemoryAllocationLib.h>
20 #include <ArmPlatform.h>
21
22 // Number of Virtual Memory Map Descriptors without a Logic Tile
23 #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 4
24
25 // DDR attributes
26 #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
27 #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
28
29 /**
30 Return the Virtual Memory Map of your platform
31
32 This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
33
34 @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
35 Virtual Memory mapping. This array must be ended by a zero-filled
36 entry
37
38 **/
39 VOID
40 ArmPlatformGetVirtualMemoryMap (
41 IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
42 )
43 {
44 ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
45 UINTN Index = 0;
46 ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
47
48 ASSERT(VirtualMemoryMap != NULL);
49
50 VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
51 if (VirtualMemoryTable == NULL) {
52 return;
53 }
54
55 if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
56 CacheAttributes = DDR_ATTRIBUTES_CACHED;
57 } else {
58 CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
59 }
60
61 // DDR
62 VirtualMemoryTable[Index].PhysicalBase = ARM_VE_DRAM_BASE;
63 VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE;
64 VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ;
65 VirtualMemoryTable[Index].Attributes = CacheAttributes;
66
67 // CPU peripherals. TRM. Manual says not all of them are implemented.
68 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ON_CHIP_PERIPH_BASE;
69 VirtualMemoryTable[Index].VirtualBase = ARM_VE_ON_CHIP_PERIPH_BASE;
70 VirtualMemoryTable[Index].Length = ARM_VE_ON_CHIP_PERIPH_SZ;
71 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
72
73 // Peripheral CS2 and CS3
74 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;
75 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;
76 VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ;
77 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
78
79 // End of Table
80 VirtualMemoryTable[++Index].PhysicalBase = 0;
81 VirtualMemoryTable[Index].VirtualBase = 0;
82 VirtualMemoryTable[Index].Length = 0;
83 VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
84
85 *VirtualMemoryMap = VirtualMemoryTable;
86 }