3 * Copyright (c) 2011-2014, ARM Limited. All rights reserved.
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include <Library/ArmPlatformLib.h>
16 #include <Library/DebugLib.h>
17 #include <Library/HobLib.h>
18 #include <Library/PcdLib.h>
19 #include <Library/IoLib.h>
20 #include <Library/MemoryAllocationLib.h>
21 #include <ArmPlatform.h>
23 // Number of Virtual Memory Map Descriptors
24 #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6
27 #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
28 #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
31 Return the Virtual Memory Map of your platform
33 This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
35 @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
36 Virtual Memory mapping. This array must be ended by a zero-filled
41 ArmPlatformGetVirtualMemoryMap (
42 IN ARM_MEMORY_REGION_DESCRIPTOR
** VirtualMemoryMap
45 ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes
;
46 EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes
;
48 ARM_MEMORY_REGION_DESCRIPTOR
*VirtualMemoryTable
;
50 BOOLEAN HasSparseMemory
;
51 EFI_VIRTUAL_ADDRESS SparseMemoryBase
;
52 UINT64 SparseMemorySize
;
54 ASSERT (VirtualMemoryMap
!= NULL
);
56 // The FVP model has Sparse memory
57 SysId
= MmioRead32 (ARM_VE_SYS_ID_REG
);
58 if (SysId
!= ARM_RTSM_SYS_ID
) {
59 HasSparseMemory
= TRUE
;
62 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
63 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
64 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
65 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
66 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
67 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
|
68 EFI_RESOURCE_ATTRIBUTE_TESTED
;
70 // Declared the additional DRAM from 2GB to 4GB
71 SparseMemoryBase
= 0x0880000000;
72 SparseMemorySize
= SIZE_2GB
;
74 BuildResourceDescriptorHob (
75 EFI_RESOURCE_SYSTEM_MEMORY
,
80 HasSparseMemory
= FALSE
;
83 VirtualMemoryTable
= (ARM_MEMORY_REGION_DESCRIPTOR
*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR
) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS
));
84 if (VirtualMemoryTable
== NULL
) {
88 if (FeaturePcdGet(PcdCacheEnable
) == TRUE
) {
89 CacheAttributes
= DDR_ATTRIBUTES_CACHED
;
91 CacheAttributes
= DDR_ATTRIBUTES_UNCACHED
;
94 // ReMap (Either NOR Flash or DRAM)
95 VirtualMemoryTable
[Index
].PhysicalBase
= ARM_VE_REMAP_BASE
;
96 VirtualMemoryTable
[Index
].VirtualBase
= ARM_VE_REMAP_BASE
;
97 VirtualMemoryTable
[Index
].Length
= ARM_VE_REMAP_SZ
;
99 if (FeaturePcdGet(PcdNorFlashRemapping
) == FALSE
) {
100 // Map the NOR Flash as Secure Memory
101 if (FeaturePcdGet(PcdCacheEnable
) == TRUE
) {
102 VirtualMemoryTable
[Index
].Attributes
= DDR_ATTRIBUTES_CACHED
;
104 VirtualMemoryTable
[Index
].Attributes
= DDR_ATTRIBUTES_UNCACHED
;
108 VirtualMemoryTable
[Index
].Attributes
= CacheAttributes
;
112 VirtualMemoryTable
[++Index
].PhysicalBase
= ARM_VE_DRAM_BASE
;
113 VirtualMemoryTable
[Index
].VirtualBase
= ARM_VE_DRAM_BASE
;
114 VirtualMemoryTable
[Index
].Length
= ARM_VE_DRAM_SZ
;
115 VirtualMemoryTable
[Index
].Attributes
= CacheAttributes
;
117 // CPU peripherals. TRM. Manual says not all of them are implemented.
118 VirtualMemoryTable
[++Index
].PhysicalBase
= ARM_VE_ON_CHIP_PERIPH_BASE
;
119 VirtualMemoryTable
[Index
].VirtualBase
= ARM_VE_ON_CHIP_PERIPH_BASE
;
120 VirtualMemoryTable
[Index
].Length
= ARM_VE_ON_CHIP_PERIPH_SZ
;
121 VirtualMemoryTable
[Index
].Attributes
= ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
;
123 // SMB CS0-CS1 - NOR Flash 1 & 2
124 VirtualMemoryTable
[++Index
].PhysicalBase
= ARM_VE_SMB_NOR0_BASE
;
125 VirtualMemoryTable
[Index
].VirtualBase
= ARM_VE_SMB_NOR0_BASE
;
126 VirtualMemoryTable
[Index
].Length
= ARM_VE_SMB_NOR0_SZ
+ ARM_VE_SMB_NOR1_SZ
;
127 VirtualMemoryTable
[Index
].Attributes
= ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
;
130 VirtualMemoryTable
[++Index
].PhysicalBase
= ARM_VE_SMB_SRAM_BASE
;
131 VirtualMemoryTable
[Index
].VirtualBase
= ARM_VE_SMB_SRAM_BASE
;
132 VirtualMemoryTable
[Index
].Length
= ARM_VE_SMB_SRAM_SZ
;
133 VirtualMemoryTable
[Index
].Attributes
= CacheAttributes
;
135 // Peripheral CS2 and CS3
136 VirtualMemoryTable
[++Index
].PhysicalBase
= ARM_VE_SMB_PERIPH_BASE
;
137 VirtualMemoryTable
[Index
].VirtualBase
= ARM_VE_SMB_PERIPH_BASE
;
138 VirtualMemoryTable
[Index
].Length
= 2 * ARM_VE_SMB_PERIPH_SZ
;
139 VirtualMemoryTable
[Index
].Attributes
= ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
;
141 // Map sparse memory region if present
142 if (HasSparseMemory
) {
143 VirtualMemoryTable
[++Index
].PhysicalBase
= SparseMemoryBase
;
144 VirtualMemoryTable
[Index
].VirtualBase
= SparseMemoryBase
;
145 VirtualMemoryTable
[Index
].Length
= SparseMemorySize
;
146 VirtualMemoryTable
[Index
].Attributes
= CacheAttributes
;
150 VirtualMemoryTable
[++Index
].PhysicalBase
= 0;
151 VirtualMemoryTable
[Index
].VirtualBase
= 0;
152 VirtualMemoryTable
[Index
].Length
= 0;
153 VirtualMemoryTable
[Index
].Attributes
= (ARM_MEMORY_REGION_ATTRIBUTES
)0;
155 *VirtualMemoryMap
= VirtualMemoryTable
;