ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.h

   1 /** @file
   2   Header for the MMC Host Protocol implementation for the ARM PrimeCell PL180.
   3
   4   Copyright (c) 2011-2012, ARM Limited. All rights reserved.
   5
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #ifndef __PL180_MCI_H
  11 #define __PL180_MCI_H
  12
  13 #include <Uefi.h>
  14
  15 #include <Protocol/MmcHost.h>
  16
  17 #include <Library/UefiLib.h>
  18 #include <Library/DebugLib.h>
  19 #include <Library/UefiBootServicesTableLib.h>
  20 #include <Library/IoLib.h>
  21 #include <Library/TimerLib.h>
  22 #include <Library/PcdLib.h>
  23
  24 #define PL180_MCI_DXE_VERSION           0x10
  25
  26 #define MCI_SYSCTL  FixedPcdGet32 (PcdPL180MciBaseAddress)
  27
  28 #define MCI_POWER_CONTROL_REG           (MCI_SYSCTL + 0x000)
  29 #define MCI_CLOCK_CONTROL_REG           (MCI_SYSCTL + 0x004)
  30 #define MCI_ARGUMENT_REG                (MCI_SYSCTL + 0x008)
  31 #define MCI_COMMAND_REG                 (MCI_SYSCTL + 0x00C)
  32 #define MCI_RESPCMD_REG                 (MCI_SYSCTL + 0x010)
  33 #define MCI_RESPONSE3_REG               (MCI_SYSCTL + 0x014)
  34 #define MCI_RESPONSE2_REG               (MCI_SYSCTL + 0x018)
  35 #define MCI_RESPONSE1_REG               (MCI_SYSCTL + 0x01C)
  36 #define MCI_RESPONSE0_REG               (MCI_SYSCTL + 0x020)
  37 #define MCI_DATA_TIMER_REG              (MCI_SYSCTL + 0x024)
  38 #define MCI_DATA_LENGTH_REG             (MCI_SYSCTL + 0x028)
  39 #define MCI_DATA_CTL_REG                (MCI_SYSCTL + 0x02C)
  40 #define MCI_DATA_COUNTER                (MCI_SYSCTL + 0x030)
  41 #define MCI_STATUS_REG                  (MCI_SYSCTL + 0x034)
  42 #define MCI_CLEAR_STATUS_REG            (MCI_SYSCTL + 0x038)
  43 #define MCI_INT0_MASK_REG               (MCI_SYSCTL + 0x03C)
  44 #define MCI_INT1_MASK_REG               (MCI_SYSCTL + 0x040)
  45 #define MCI_SELECT_REG                  (MCI_SYSCTL + 0x044)
  46 #define MCI_FIFOCOUNT_REG               (MCI_SYSCTL + 0x048)
  47 #define MCI_FIFO_REG                    (MCI_SYSCTL + 0x080)
  48 #define MCI_PERIPH_ID_REG0              (MCI_SYSCTL + 0xFE0)
  49 #define MCI_PERIPH_ID_REG1              (MCI_SYSCTL + 0xFE4)
  50 #define MCI_PERIPH_ID_REG2              (MCI_SYSCTL + 0xFE8)
  51 #define MCI_PERIPH_ID_REG3              (MCI_SYSCTL + 0xFEC)
  52 #define MCI_PCELL_ID_REG0               (MCI_SYSCTL + 0xFF0)
  53 #define MCI_PCELL_ID_REG1               (MCI_SYSCTL + 0xFF4)
  54 #define MCI_PCELL_ID_REG2               (MCI_SYSCTL + 0xFF8)
  55 #define MCI_PCELL_ID_REG3               (MCI_SYSCTL + 0xFFC)
  56
  57 #define MCI_PERIPH_ID0                  0x80
  58 #define MCI_PERIPH_ID1                  0x11
  59 #define MCI_PERIPH_ID2                  0x04
  60 #define MCI_PERIPH_ID3                  0x00
  61 #define MCI_PCELL_ID0                   0x0D
  62 #define MCI_PCELL_ID1                   0xF0
  63 #define MCI_PCELL_ID2                   0x05
  64 #define MCI_PCELL_ID3                   0xB1
  65
  66 #define MCI_POWER_OFF                   0
  67 #define MCI_POWER_UP                    BIT1
  68 #define MCI_POWER_ON                    (BIT1 | BIT0)
  69 #define MCI_POWER_OPENDRAIN             BIT6
  70 #define MCI_POWER_ROD                   BIT7
  71
  72 #define MCI_CLOCK_ENABLE                BIT8
  73 #define MCI_CLOCK_POWERSAVE             BIT9
  74 #define MCI_CLOCK_BYPASS                BIT10
  75 #define MCI_CLOCK_WIDEBUS               BIT11
  76
  77 #define MCI_STATUS_CMD_CMDCRCFAIL       BIT0
  78 #define MCI_STATUS_CMD_DATACRCFAIL      BIT1
  79 #define MCI_STATUS_CMD_CMDTIMEOUT       BIT2
  80 #define MCI_STATUS_CMD_DATATIMEOUT      BIT3
  81 #define MCI_STATUS_CMD_TX_UNDERRUN      BIT4
  82 #define MCI_STATUS_CMD_RXOVERRUN        BIT5
  83 #define MCI_STATUS_CMD_RESPEND          BIT6
  84 #define MCI_STATUS_CMD_SENT             BIT7
  85 #define MCI_STATUS_CMD_DATAEND          BIT8
  86 #define MCI_STATUS_CMD_START_BIT_ERROR  BIT9
  87 #define MCI_STATUS_CMD_DATABLOCKEND     BIT10
  88 #define MCI_STATUS_CMD_ACTIVE           BIT11
  89 #define MCI_STATUS_CMD_TXACTIVE         BIT12
  90 #define MCI_STATUS_CMD_RXACTIVE         BIT13
  91 #define MCI_STATUS_CMD_TXFIFOHALFEMPTY  BIT14
  92 #define MCI_STATUS_CMD_RXFIFOHALFFULL   BIT15
  93 #define MCI_STATUS_CMD_TXFIFOFULL       BIT16
  94 #define MCI_STATUS_CMD_RXFIFOFULL       BIT17
  95 #define MCI_STATUS_CMD_TXFIFOEMPTY      BIT18
  96 #define MCI_STATUS_CMD_RXFIFOEMPTY      BIT19
  97 #define MCI_STATUS_CMD_TXDATAAVAILBL    BIT20
  98 #define MCI_STATUS_CMD_RXDATAAVAILBL    BIT21
  99
 100 #define MCI_STATUS_TXDONE               (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)
 101 #define MCI_STATUS_RXDONE               (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)
 102 #define MCI_STATUS_READ_ERROR           (  MCI_STATUS_CMD_DATACRCFAIL     \
 103                                          | MCI_STATUS_CMD_DATATIMEOUT     \
 104                                          | MCI_STATUS_CMD_RXOVERRUN       \
 105                                          | MCI_STATUS_CMD_START_BIT_ERROR )
 106 #define MCI_STATUS_WRITE_ERROR          (  MCI_STATUS_CMD_DATACRCFAIL \
 107                                          | MCI_STATUS_CMD_DATATIMEOUT \
 108                                          | MCI_STATUS_CMD_TX_UNDERRUN )
 109 #define MCI_STATUS_CMD_ERROR            (  MCI_STATUS_CMD_CMDCRCFAIL      \
 110                                          | MCI_STATUS_CMD_CMDTIMEOUT      \
 111                                          | MCI_STATUS_CMD_START_BIT_ERROR )
 112
 113 #define MCI_CLR_CMD_STATUS              (  MCI_STATUS_CMD_RESPEND \
 114                                          | MCI_STATUS_CMD_SENT    \
 115                                          | MCI_STATUS_CMD_ERROR )
 116
 117 #define MCI_CLR_READ_STATUS             (  MCI_STATUS_RXDONE     \
 118                                          | MCI_STATUS_READ_ERROR )
 119
 120 #define MCI_CLR_WRITE_STATUS            (  MCI_STATUS_TXDONE      \
 121                                          | MCI_STATUS_WRITE_ERROR )
 122
 123 #define MCI_CLR_ALL_STATUS              (BIT11 - 1)
 124
 125 #define MCI_DATACTL_DISABLE_MASK        0xFE
 126 #define MCI_DATACTL_ENABLE              BIT0
 127 #define MCI_DATACTL_CONT_TO_CARD        0
 128 #define MCI_DATACTL_CARD_TO_CONT        BIT1
 129 #define MCI_DATACTL_BLOCK_TRANS         0
 130 #define MCI_DATACTL_STREAM_TRANS        BIT2
 131 #define MCI_DATACTL_DMA_DISABLED        0
 132 #define MCI_DATACTL_DMA_ENABLE          BIT3
 133
 134 #define INDX_MASK                       0x3F
 135
 136 #define MCI_CPSM_WAIT_RESPONSE          BIT6
 137 #define MCI_CPSM_LONG_RESPONSE          BIT7
 138 #define MCI_CPSM_LONG_INTERRUPT         BIT8
 139 #define MCI_CPSM_LONG_PENDING           BIT9
 140 #define MCI_CPSM_ENABLE                 BIT10
 141
 142 #define MCI_TRACE(txt)                  DEBUG ((EFI_D_BLKIO, "ARM_MCI: " txt "\n"))
 143
 144 EFI_STATUS
 145 EFIAPI
 146 MciGetDriverName (
 147   IN  EFI_COMPONENT_NAME_PROTOCOL  *This,
 148   IN  CHAR8                        *Language,
 149   OUT CHAR16                       **DriverName
 150   );
 151
 152 EFI_STATUS
 153 EFIAPI
 154 MciGetControllerName (
 155   IN  EFI_COMPONENT_NAME_PROTOCOL                     *This,
 156   IN  EFI_HANDLE                                      ControllerHandle,
 157   IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,
 158   IN  CHAR8                                           *Language,
 159   OUT CHAR16                                          **ControllerName
 160   );
 161
 162 #endif