ArmPlatformPkg/Include/Drivers/PL35xSmc.h

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #ifndef PL35xSMC_H_
  16 #define PL35xSMC_H_
  17
  18 #define PL350_SMC_DIRECT_CMD_OFFSET  0x10
  19 #define PL350_SMC_SET_CYCLES_OFFSET  0x14
  20 #define PL350_SMC_SET_OPMODE_OFFSET  0x18
  21
  22 #define PL350_SMC_DIRECT_CMD_ADDR(addr)                 ((addr) & 0xFFFFF)
  23 #define PL350_SMC_DIRECT_CMD_ADDR_SET_CRE               (1 << 20)
  24 #define PL350_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE       (3 << 21)
  25 #define PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE            (2 << 21)
  26 #define PL350_SMC_DIRECT_CMD_ADDR_CMD_MODE              (1 << 21)
  27 #define PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI        (0 << 21)
  28 #define PL350_SMC_DIRECT_CMD_ADDR_CS_INTERF(interf,chip) (((interf) << 25) | ((chip) << 23))
  29 #define PL350_SMC_DIRECT_CMD_ADDR_CS(ChipSelect)        (((ChipSelect) & 0x7) << 23)
  30
  31 #define PL350_SMC_SET_OPMODE_MEM_WIDTH_8                (0 << 0)
  32 #define PL350_SMC_SET_OPMODE_MEM_WIDTH_16               (1 << 0)
  33 #define PL350_SMC_SET_OPMODE_MEM_WIDTH_32               (2 << 0)
  34 #define PL350_SMC_SET_OPMODE_SET_RD_SYNC                (1 << 2)
  35 #define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1      (0 << 3)
  36 #define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4      (1 << 3)
  37 #define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8      (2 << 3)
  38 #define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16     (3 << 3)
  39 #define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32     (4 << 3)
  40 #define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT   (5 << 3)
  41 #define PL350_SMC_SET_OPMODE_SET_WR_SYNC                (1 << 6)
  42 #define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1      (0 << 7)
  43 #define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4      (1 << 7)
  44 #define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8      (2 << 7)
  45 #define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16     (3 << 7)
  46 #define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32     (4 << 7)
  47 #define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT   (5 << 7)
  48 #define PL350_SMC_SET_OPMODE_SET_BAA                    (1 << 10)
  49 #define PL350_SMC_SET_OPMODE_SET_ADV                    (1 << 11)
  50 #define PL350_SMC_SET_OPMODE_SET_BLS                    (1 << 12)
  51 #define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY        (0 << 13)
  52 #define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_32         (1 << 13)
  53 #define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_64         (2 << 13)
  54 #define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_128        (3 << 13)
  55 #define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_256        (4 << 13)
  56
  57 #define PL350_SMC_SET_CYCLE_NAND_T_RC(t)                (((t) & 0xF) << 0)
  58 #define PL350_SMC_SET_CYCLE_NAND_T_WC(t)                (((t) & 0xF) << 4)
  59 #define PL350_SMC_SET_CYCLE_NAND_T_REA(t)              (((t) & 0x7) << 8)
  60 #define PL350_SMC_SET_CYCLE_NAND_T_WP(t)                (((t) & 0x7) << 11)
  61 #define PL350_SMC_SET_CYCLE_NAND_T_CLR(t)                (((t) & 0x7) << 14)
  62 #define PL350_SMC_SET_CYCLE_NAND_T_AR(t)                (((t) & 0x7) << 17)
  63 #define PL350_SMC_SET_CYCLE_NAND_T_RR(t)                (((t) & 0x7) << 20)
  64
  65 #define PL350_SMC_SET_CYCLE_SRAM_T_RC(t)                (((t) & 0xF) << 0)
  66 #define PL350_SMC_SET_CYCLE_SRAM_T_WC(t)                (((t) & 0xF) << 4)
  67 #define PL350_SMC_SET_CYCLE_SRAM_T_CEOE(t)              (((t) & 0x7) << 8)
  68 #define PL350_SMC_SET_CYCLE_SRAM_T_WP(t)                (((t) & 0x7) << 11)
  69 #define PL350_SMC_SET_CYCLE_SRAM_T_PC(t)                (((t) & 0x7) << 14)
  70 #define PL350_SMC_SET_CYCLE_SRAM_T_TR(t)                (((t) & 0x7) << 17)
  71 #define PL350_SMC_SET_CYCLE_SRAM_WE_TIME                (1 << 20)
  72
  73 #endif