3 * Copyright (c) 2011, ARM Limited. All rights reserved.
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include <Library/DebugLib.h>
18 #include <Library/PcdLib.h>
19 #include <Library/PrintLib.h>
20 #include <Library/SerialPortLib.h>
21 #include <Chipset/ArmV7.h>
22 #include <Drivers/PL390Gic.h>
24 #define ARM_PRIMARY_CORE 0
26 // When the firmware is built as not Standalone, the secondary cores need to wait the firmware
27 // entirely written into DRAM. It is the firmware from DRAM which will wake up the secondary cores.
29 NonSecureWaitForFirmware (
33 VOID (*secondary_start
)(VOID
);
35 // The secondary cores will execute the firmware once wake from WFI.
36 secondary_start
= (VOID (*)())PcdGet32(PcdNormalFvBaseAddress
);
40 // Acknowledge the interrupt and send End of Interrupt signal.
41 PL390GicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase
), ARM_PRIMARY_CORE
);
43 // Jump to secondary core entry point.
46 // PEI Core should always load and never return
51 Call before jumping to Normal World
53 This function allows the firmware platform to do extra actions before
54 jumping to the Normal World
58 ArmPlatformSecExtraAction (
60 OUT UINTN
* JumpAddress
66 if (FeaturePcdGet (PcdStandalone
) == FALSE
) {
67 if (CoreId
== ARM_PRIMARY_CORE
) {
68 UINTN
* StartAddress
= (UINTN
*)PcdGet32(PcdNormalFvBaseAddress
);
70 // Patch the DRAM to make an infinite loop at the start address
71 *StartAddress
= 0xEAFFFFFE; // opcode for while(1)
73 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"Waiting for firmware at 0x%08X ...\n\r",StartAddress
);
74 SerialPortWrite ((UINT8
*) Buffer
, CharCount
);
76 *JumpAddress
= PcdGet32(PcdNormalFvBaseAddress
);
78 // When the primary core is stopped by the hardware debugger to copy the firmware
79 // into DRAM. The secondary cores are still running. As soon as the first bytes of
80 // the firmware are written into DRAM, the secondary cores will start to execute the
81 // code even if the firmware is not entirely written into the memory.
82 // That's why the secondary cores need to be parked in WFI and wake up once the
85 *JumpAddress
= (UINTN
)NonSecureWaitForFirmware
;
87 } else if (FeaturePcdGet (PcdSystemMemoryInitializeInSec
)) {
88 if (CoreId
== ARM_PRIMARY_CORE
) {
89 // Signal the secondary cores they can jump to PEI phase
90 PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase
), GIC_ICDSGIR_FILTER_EVERYONEELSE
, 0x0E);
92 // To enter into Non Secure state, we need to make a return from exception
93 *JumpAddress
= PcdGet32(PcdNormalFvBaseAddress
);
95 // We wait for the primary core to finish to initialize the System Memory. Otherwise the secondary
96 // cores would make crash the system by setting their stacks in DRAM before the primary core has not
97 // finished to initialize the system memory.
98 *JumpAddress
= (UINTN
)NonSecureWaitForFirmware
;
101 *JumpAddress
= PcdGet32(PcdNormalFvBaseAddress
);