ArmPlatformPkg/Library/HdLcd/HdLcd.h

   1 /** @file
   2
   3  Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>
   4
   5  This program and the accompanying materials
   6  are licensed and made available under the terms and conditions of the BSD License
   7  which accompanies this distribution.  The full text of the license may be found at
   8  http://opensource.org/licenses/bsd-license.php
   9
  10  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13  **/
  14
  15 #ifndef HDLCD_H_
  16 #define HDLCD_H_
  17
  18 // HDLCD Controller Register Offsets
  19 #define HDLCD_REG_VERSION                 ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)
  20 #define HDLCD_REG_INT_RAWSTAT             ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)
  21 #define HDLCD_REG_INT_CLEAR               ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)
  22 #define HDLCD_REG_INT_MASK                ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)
  23 #define HDLCD_REG_INT_STATUS              ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)
  24 #define HDLCD_REG_FB_BASE                 ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)
  25 #define HDLCD_REG_FB_LINE_LENGTH          ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)
  26 #define HDLCD_REG_FB_LINE_COUNT           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)
  27 #define HDLCD_REG_FB_LINE_PITCH           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)
  28 #define HDLCD_REG_BUS_OPTIONS             ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)
  29 #define HDLCD_REG_V_SYNC                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)
  30 #define HDLCD_REG_V_BACK_PORCH            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)
  31 #define HDLCD_REG_V_DATA                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)
  32 #define HDLCD_REG_V_FRONT_PORCH           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)
  33 #define HDLCD_REG_H_SYNC                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)
  34 #define HDLCD_REG_H_BACK_PORCH            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)
  35 #define HDLCD_REG_H_DATA                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)
  36 #define HDLCD_REG_H_FRONT_PORCH           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)
  37 #define HDLCD_REG_POLARITIES              ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)
  38 #define HDLCD_REG_COMMAND                 ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)
  39 #define HDLCD_REG_PIXEL_FORMAT            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)
  40 #define HDLCD_REG_RED_SELECT              ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)
  41 #define HDLCD_REG_GREEN_SELECT            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)
  42 #define HDLCD_REG_BLUE_SELECT             ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)
  43
  44 // HDLCD Values of registers
  45
  46 // HDLCD Interrupt mask, clear and status register
  47 #define HDLCD_DMA_END                     BIT0    /* DMA has finished reading a frame */
  48 #define HDLCD_BUS_ERROR                   BIT1    /* DMA bus error */
  49 #define HDLCD_SYNC                        BIT2    /* Vertical sync */
  50 #define HDLCD_UNDERRUN                    BIT3    /* No Data available while DATAEN active */
  51
  52 // CLCD_CONTROL Control register
  53 #define HDLCD_DISABLE                     0
  54 #define HDLCD_ENABLE                      BIT0
  55
  56 // Bus Options
  57 #define HDLCD_BURST_1                     BIT0
  58 #define HDLCD_BURST_2                     BIT1
  59 #define HDLCD_BURST_4                     BIT2
  60 #define HDLCD_BURST_8                     BIT3
  61 #define HDLCD_BURST_16                    BIT4
  62
  63 // Polarities - HIGH
  64 #define HDLCD_VSYNC_HIGH                  BIT0
  65 #define HDLCD_HSYNC_HIGH                  BIT1
  66 #define HDLCD_DATEN_HIGH                  BIT2
  67 #define HDLCD_DATA_HIGH                   BIT3
  68 #define HDLCD_PXCLK_HIGH                  BIT4
  69 // Polarities - LOW (for completion and for ease of understanding the hardware settings)
  70 #define HDLCD_VSYNC_LOW                   0
  71 #define HDLCD_HSYNC_LOW                   0
  72 #define HDLCD_DATEN_LOW                   0
  73 #define HDLCD_DATA_LOW                    0
  74 #define HDLCD_PXCLK_LOW                   0
  75
  76 // Default polarities
  77 #define HDLCD_DEFAULT_POLARITIES   (HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH |       \
  78                                     HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW |      \
  79                                     HDLCD_VSYNC_HIGH)
  80
  81 // Pixel Format
  82 #define HDLCD_LITTLE_ENDIAN              (0 << 31)
  83 #define HDLCD_BIG_ENDIAN                 (1 << 31)
  84
  85 // Number of bytes per pixel
  86 #define HDLCD_4BYTES_PER_PIXEL           ((4 - 1) << 3)
  87
  88 #define HDLCD_PRODUCT_ID                 0x1CDC
  89
  90 #endif /* HDLCD_H_ */