ArmPlatformPkg/Library/PL011UartLib/PL011Uart.h

   1 /** @file
   2
   3   Copyright (c) 2011-2016, ARM Limited. All rights reserved.
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 #ifndef __PL011_UART_H__
  10 #define __PL011_UART_H__
  11
  12 #define PL011_VARIANT_ZTE  1
  13
  14 // PL011 Registers
  15 #if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE
  16 #define UARTDR     0x004
  17 #define UARTRSR    0x010
  18 #define UARTECR    0x010
  19 #define UARTFR     0x014
  20 #define UARTIBRD   0x024
  21 #define UARTFBRD   0x028
  22 #define UARTLCR_H  0x030
  23 #define UARTCR     0x034
  24 #define UARTIFLS   0x038
  25 #define UARTIMSC   0x040
  26 #define UARTRIS    0x044
  27 #define UARTMIS    0x048
  28 #define UARTICR    0x04c
  29 #define UARTDMACR  0x050
  30 #else
  31 #define UARTDR     0x000
  32 #define UARTRSR    0x004
  33 #define UARTECR    0x004
  34 #define UARTFR     0x018
  35 #define UARTILPR   0x020
  36 #define UARTIBRD   0x024
  37 #define UARTFBRD   0x028
  38 #define UARTLCR_H  0x02C
  39 #define UARTCR     0x030
  40 #define UARTIFLS   0x034
  41 #define UARTIMSC   0x038
  42 #define UARTRIS    0x03C
  43 #define UARTMIS    0x040
  44 #define UARTICR    0x044
  45 #define UARTDMACR  0x048
  46 #endif
  47
  48 #define UARTPID0  0xFE0
  49 #define UARTPID1  0xFE4
  50 #define UARTPID2  0xFE8
  51 #define UARTPID3  0xFEC
  52
  53 // Data status bits
  54 #define UART_DATA_ERROR_MASK  0x0F00
  55
  56 // Status reg bits
  57 #define UART_STATUS_ERROR_MASK  0x0F
  58
  59 // Flag reg bits
  60 #if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE
  61 #define PL011_UARTFR_RI    (1 << 0)         // Ring indicator
  62 #define PL011_UARTFR_TXFE  (1 << 7)         // Transmit FIFO empty
  63 #define PL011_UARTFR_RXFF  (1 << 6)         // Receive  FIFO full
  64 #define PL011_UARTFR_TXFF  (1 << 5)         // Transmit FIFO full
  65 #define PL011_UARTFR_RXFE  (1 << 4)         // Receive  FIFO empty
  66 #define PL011_UARTFR_BUSY  (1 << 8)         // UART busy
  67 #define PL011_UARTFR_DCD   (1 << 2)         // Data carrier detect
  68 #define PL011_UARTFR_DSR   (1 << 3)         // Data set ready
  69 #define PL011_UARTFR_CTS   (1 << 1)         // Clear to send
  70 #else
  71 #define PL011_UARTFR_RI    (1 << 8)         // Ring indicator
  72 #define PL011_UARTFR_TXFE  (1 << 7)         // Transmit FIFO empty
  73 #define PL011_UARTFR_RXFF  (1 << 6)         // Receive  FIFO full
  74 #define PL011_UARTFR_TXFF  (1 << 5)         // Transmit FIFO full
  75 #define PL011_UARTFR_RXFE  (1 << 4)         // Receive  FIFO empty
  76 #define PL011_UARTFR_BUSY  (1 << 3)         // UART busy
  77 #define PL011_UARTFR_DCD   (1 << 2)         // Data carrier detect
  78 #define PL011_UARTFR_DSR   (1 << 1)         // Data set ready
  79 #define PL011_UARTFR_CTS   (1 << 0)         // Clear to send
  80 #endif
  81
  82 // Flag reg bits - alternative names
  83 #define UART_TX_EMPTY_FLAG_MASK  PL011_UARTFR_TXFE
  84 #define UART_RX_FULL_FLAG_MASK   PL011_UARTFR_RXFF
  85 #define UART_TX_FULL_FLAG_MASK   PL011_UARTFR_TXFF
  86 #define UART_RX_EMPTY_FLAG_MASK  PL011_UARTFR_RXFE
  87 #define UART_BUSY_FLAG_MASK      PL011_UARTFR_BUSY
  88
  89 // Control reg bits
  90 #define PL011_UARTCR_CTSEN   (1 << 15)      // CTS hardware flow control enable
  91 #define PL011_UARTCR_RTSEN   (1 << 14)      // RTS hardware flow control enable
  92 #define PL011_UARTCR_RTS     (1 << 11)      // Request to send
  93 #define PL011_UARTCR_DTR     (1 << 10)      // Data transmit ready.
  94 #define PL011_UARTCR_RXE     (1 << 9)       // Receive enable
  95 #define PL011_UARTCR_TXE     (1 << 8)       // Transmit enable
  96 #define PL011_UARTCR_LBE     (1 << 7)       // Loopback enable
  97 #define PL011_UARTCR_UARTEN  (1 << 0)       // UART Enable
  98
  99 // Line Control Register Bits
 100 #define PL011_UARTLCR_H_SPS     (1 << 7)    // Stick parity select
 101 #define PL011_UARTLCR_H_WLEN_8  (3 << 5)
 102 #define PL011_UARTLCR_H_WLEN_7  (2 << 5)
 103 #define PL011_UARTLCR_H_WLEN_6  (1 << 5)
 104 #define PL011_UARTLCR_H_WLEN_5  (0 << 5)
 105 #define PL011_UARTLCR_H_FEN     (1 << 4)    // FIFOs Enable
 106 #define PL011_UARTLCR_H_STP2    (1 << 3)    // Two stop bits select
 107 #define PL011_UARTLCR_H_EPS     (1 << 2)    // Even parity select
 108 #define PL011_UARTLCR_H_PEN     (1 << 1)    // Parity Enable
 109 #define PL011_UARTLCR_H_BRK     (1 << 0)    // Send break
 110
 111 #define PL011_UARTPID2_VER(X)  (((X) >> 4) & 0xF)
 112 #define PL011_VER_R1P4  0x2
 113
 114 #endif