3 * Copyright (c) 2011, ARM Limited. All rights reserved.
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include <Library/ArmGicLib.h>
18 #include <Library/ArmMPCoreMailBoxLib.h>
19 #include <Chipset/ArmV7.h>
23 IN UINTN UefiMemoryBase
,
25 IN UINTN GlobalVariableBase
,
26 IN UINT64 StartTimeStamp
29 // Enable the GIC Distributor
30 ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase
));
32 // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader toresume their initialization
33 if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores
)) {
34 // Sending SGI to all the Secondary CPU interfaces
35 ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase
), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE
, 0x0E);
38 PrePiMain (UefiMemoryBase
, StacksBase
, GlobalVariableBase
, StartTimeStamp
);
40 // We must never return
49 // Function pointer to Secondary Core entry point
50 VOID (*secondary_start
)(VOID
);
51 UINTN secondary_entry_addr
=0;
53 // Clear Secondary cores MailBox
54 ArmClearMPCoreMailbox();
56 while (secondary_entry_addr
= ArmGetMPCoreMailbox(), secondary_entry_addr
== 0) {
58 // Acknowledge the interrupt and send End of Interrupt signal.
59 ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase
), PRIMARY_CORE_ID
);
62 secondary_start
= (VOID (*)())secondary_entry_addr
;
64 // Jump to secondary core entry point.
67 // The secondaries shouldn't reach here