ArmPlatformPkg/PrePi/MainMPCore.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include "PrePi.h"
  16
  17 #include <Library/ArmGicLib.h>
  18
  19 #include <Ppi/ArmMpCoreInfo.h>
  20
  21 VOID
  22 PrimaryMain (
  23   IN  UINTN                     UefiMemoryBase,
  24   IN  UINTN                     StacksBase,
  25   IN  UINTN                     GlobalVariableBase,
  26   IN  UINT64                    StartTimeStamp
  27   )
  28 {
  29   // Enable the GIC Distributor
  30   ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));
  31
  32   // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader to resume their initialization
  33   if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {
  34     // Sending SGI to all the Secondary CPU interfaces
  35     ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
  36   }
  37
  38   PrePiMain (UefiMemoryBase, StacksBase, GlobalVariableBase, StartTimeStamp);
  39
  40   // We must never return
  41   ASSERT(FALSE);
  42 }
  43
  44 VOID
  45 SecondaryMain (
  46   IN  UINTN                     MpId
  47   )
  48 {
  49   EFI_STATUS              Status;
  50   ARM_MP_CORE_INFO_PPI    *ArmMpCoreInfoPpi;
  51   UINTN                   Index;
  52   UINTN                   ArmCoreCount;
  53   ARM_CORE_INFO           *ArmCoreInfoTable;
  54   UINT32                  ClusterId;
  55   UINT32                  CoreId;
  56   VOID                    (*SecondaryStart)(VOID);
  57   UINTN                   SecondaryEntryAddr;
  58   UINTN                   AcknowledgeInterrupt;
  59   UINTN                   InterruptId;
  60
  61   ClusterId = GET_CLUSTER_ID(MpId);
  62   CoreId    = GET_CORE_ID(MpId);
  63
  64   // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)
  65   Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);
  66   ASSERT_EFI_ERROR (Status);
  67
  68   ArmCoreCount = 0;
  69   Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
  70   ASSERT_EFI_ERROR (Status);
  71
  72   // Find the core in the ArmCoreTable
  73   for (Index = 0; Index < ArmCoreCount; Index++) {
  74     if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {
  75       break;
  76     }
  77   }
  78
  79   // The ARM Core Info Table must define every core
  80   ASSERT (Index != ArmCoreCount);
  81
  82   // Clear Secondary cores MailBox
  83   MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);
  84
  85   do {
  86     ArmCallWFI ();
  87
  88     // Read the Mailbox
  89     SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);
  90
  91     // Acknowledge the interrupt and send End of Interrupt signal.
  92     AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), &InterruptId);
  93     // Check if it is a valid interrupt ID
  94     if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {
  95       // Got a valid SGI number hence signal End of Interrupt
  96       ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);
  97     }
  98   } while (SecondaryEntryAddr == 0);
  99
 100   // Jump to secondary core entry point.
 101   SecondaryStart = (VOID (*)())SecondaryEntryAddr;
 102   SecondaryStart();
 103
 104   // The secondaries shouldn't reach here
 105   ASSERT(FALSE);
 106 }