ArmPlatformPkg/PrePi/MainMPCore.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include "PrePi.h"
  16
  17 #include <Library/ArmGicLib.h>
  18
  19 #include <Ppi/ArmMpCoreInfo.h>
  20
  21 VOID
  22 PrimaryMain (
  23   IN  UINTN                     UefiMemoryBase,
  24   IN  UINTN                     StacksBase,
  25   IN  UINTN                     GlobalVariableBase,
  26   IN  UINT64                    StartTimeStamp
  27   )
  28 {
  29   // Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0
  30   DEBUG_CODE_BEGIN();
  31   if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {
  32     DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));
  33   }
  34   DEBUG_CODE_END();
  35
  36   // Enable the GIC Distributor
  37   ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));
  38
  39   // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader to resume their initialization
  40   if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {
  41     // Sending SGI to all the Secondary CPU interfaces
  42     ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
  43   }
  44
  45   PrePiMain (UefiMemoryBase, StacksBase, GlobalVariableBase, StartTimeStamp);
  46
  47   // We must never return
  48   ASSERT(FALSE);
  49 }
  50
  51 VOID
  52 SecondaryMain (
  53   IN  UINTN                     MpId
  54   )
  55 {
  56   EFI_STATUS              Status;
  57   ARM_MP_CORE_INFO_PPI    *ArmMpCoreInfoPpi;
  58   UINTN                   Index;
  59   UINTN                   ArmCoreCount;
  60   ARM_CORE_INFO           *ArmCoreInfoTable;
  61   UINT32                  ClusterId;
  62   UINT32                  CoreId;
  63   VOID                    (*SecondaryStart)(VOID);
  64   UINTN                   SecondaryEntryAddr;
  65
  66   ClusterId = GET_CLUSTER_ID(MpId);
  67   CoreId    = GET_CORE_ID(MpId);
  68
  69   // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)
  70   Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);
  71   ASSERT_EFI_ERROR (Status);
  72
  73   ArmCoreCount = 0;
  74   Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
  75   ASSERT_EFI_ERROR (Status);
  76
  77   // Find the core in the ArmCoreTable
  78   for (Index = 0; Index < ArmCoreCount; Index++) {
  79     if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {
  80       break;
  81     }
  82   }
  83
  84   // The ARM Core Info Table must define every core
  85   ASSERT (Index != ArmCoreCount);
  86
  87   // Clear Secondary cores MailBox
  88   MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);
  89
  90   do {
  91     ArmCallWFI ();
  92
  93     // Read the Mailbox
  94     SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);
  95
  96     // Acknowledge the interrupt and send End of Interrupt signal.
  97     ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), NULL, NULL);
  98   } while (SecondaryEntryAddr == 0);
  99
 100   // Jump to secondary core entry point.
 101   SecondaryStart = (VOID (*)())SecondaryEntryAddr;
 102   SecondaryStart();
 103
 104   // The secondaries shouldn't reach here
 105   ASSERT(FALSE);
 106 }