ArmPlatformPkg/PrePi/PrePi.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2017, ARM Limited. All rights reserved.
   4 *
   5 *  SPDX-License-Identifier: BSD-2-Clause-Patent
   6 *
   7 **/
   8
   9 #include <PiPei.h>
  10
  11 #include <Library/CacheMaintenanceLib.h>
  12 #include <Library/DebugAgentLib.h>
  13 #include <Library/PrePiLib.h>
  14 #include <Library/PrintLib.h>
  15 #include <Library/PrePiHobListPointerLib.h>
  16 #include <Library/TimerLib.h>
  17 #include <Library/PerformanceLib.h>
  18
  19 #include <Ppi/GuidedSectionExtraction.h>
  20 #include <Ppi/ArmMpCoreInfo.h>
  21 #include <Ppi/SecPerformance.h>
  22
  23 #include "PrePi.h"
  24
  25 #define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemoryEnd) || \
  26                   ((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= FixedPcdGet64 (PcdSystemMemoryBase)))
  27
  28 UINT64 mSystemMemoryEnd = FixedPcdGet64(PcdSystemMemoryBase) +
  29                           FixedPcdGet64(PcdSystemMemorySize) - 1;
  30
  31 EFI_STATUS
  32 GetPlatformPpi (
  33   IN  EFI_GUID  *PpiGuid,
  34   OUT VOID      **Ppi
  35   )
  36 {
  37   UINTN                   PpiListSize;
  38   UINTN                   PpiListCount;
  39   EFI_PEI_PPI_DESCRIPTOR  *PpiList;
  40   UINTN                   Index;
  41
  42   PpiListSize = 0;
  43   ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
  44   PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);
  45   for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
  46     if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {
  47       *Ppi = PpiList->Ppi;
  48       return EFI_SUCCESS;
  49     }
  50   }
  51
  52   return EFI_NOT_FOUND;
  53 }
  54
  55 VOID
  56 PrePiMain (
  57   IN  UINTN                     UefiMemoryBase,
  58   IN  UINTN                     StacksBase,
  59   IN  UINT64                    StartTimeStamp
  60   )
  61 {
  62   EFI_HOB_HANDOFF_INFO_TABLE*   HobList;
  63   ARM_MP_CORE_INFO_PPI*         ArmMpCoreInfoPpi;
  64   UINTN                         ArmCoreCount;
  65   ARM_CORE_INFO*                ArmCoreInfoTable;
  66   EFI_STATUS                    Status;
  67   CHAR8                         Buffer[100];
  68   UINTN                         CharCount;
  69   UINTN                         StacksSize;
  70   FIRMWARE_SEC_PERFORMANCE      Performance;
  71
  72   // If ensure the FD is either part of the System Memory or totally outside of the System Memory (XIP)
  73   ASSERT (IS_XIP() ||
  74           ((FixedPcdGet64 (PcdFdBaseAddress) >= FixedPcdGet64 (PcdSystemMemoryBase)) &&
  75            ((UINT64)(FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT64)mSystemMemoryEnd)));
  76
  77   // Initialize the architecture specific bits
  78   ArchInitialize ();
  79
  80   // Initialize the Serial Port
  81   SerialPortInitialize ();
  82   CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware (version %s built at %a on %a)\n\r",
  83     (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
  84   SerialPortWrite ((UINT8 *) Buffer, CharCount);
  85
  86   // Initialize the Debug Agent for Source Level Debugging
  87   InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
  88   SaveAndSetDebugTimerInterrupt (TRUE);
  89
  90   // Declare the PI/UEFI memory region
  91   HobList = HobConstructor (
  92     (VOID*)UefiMemoryBase,
  93     FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),
  94     (VOID*)UefiMemoryBase,
  95     (VOID*)StacksBase  // The top of the UEFI Memory is reserved for the stacks
  96     );
  97   PrePeiSetHobList (HobList);
  98
  99   // Initialize MMU and Memory HOBs (Resource Descriptor HOBs)
 100   Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));
 101   ASSERT_EFI_ERROR (Status);
 102
 103   // Create the Stacks HOB (reserve the memory for all stacks)
 104   if (ArmIsMpCore ()) {
 105     StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize) +
 106                  ((FixedPcdGet32 (PcdCoreCount) - 1) * FixedPcdGet32 (PcdCPUCoreSecondaryStackSize));
 107   } else {
 108     StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);
 109   }
 110   BuildStackHob (StacksBase, StacksSize);
 111
 112   //TODO: Call CpuPei as a library
 113   BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));
 114
 115   if (ArmIsMpCore ()) {
 116     // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid
 117     Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);
 118
 119     // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)
 120     ASSERT_EFI_ERROR (Status);
 121
 122     // Build the MP Core Info Table
 123     ArmCoreCount = 0;
 124     Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
 125     if (!EFI_ERROR(Status) && (ArmCoreCount > 0)) {
 126       // Build MPCore Info HOB
 127       BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);
 128     }
 129   }
 130
 131   // Store timer value logged at the beginning of firmware image execution
 132   Performance.ResetEnd = GetTimeInNanoSecond (StartTimeStamp);
 133
 134   // Build SEC Performance Data Hob
 135   BuildGuidDataHob (&gEfiFirmwarePerformanceGuid, &Performance, sizeof (Performance));
 136
 137   // Set the Boot Mode
 138   SetBootMode (ArmPlatformGetBootMode ());
 139
 140   // Initialize Platform HOBs (CpuHob and FvHob)
 141   Status = PlatformPeim ();
 142   ASSERT_EFI_ERROR (Status);
 143
 144   // Now, the HOB List has been initialized, we can register performance information
 145   PERF_START (NULL, "PEI", NULL, StartTimeStamp);
 146
 147   // SEC phase needs to run library constructors by hand.
 148   ProcessLibraryConstructorList ();
 149
 150   // Assume the FV that contains the SEC (our code) also contains a compressed FV.
 151   Status = DecompressFirstFv ();
 152   ASSERT_EFI_ERROR (Status);
 153
 154   // Load the DXE Core and transfer control to it
 155   Status = LoadDxeCoreFromFv (NULL, 0);
 156   ASSERT_EFI_ERROR (Status);
 157 }
 158
 159 VOID
 160 CEntryPoint (
 161   IN  UINTN                     MpId,
 162   IN  UINTN                     UefiMemoryBase,
 163   IN  UINTN                     StacksBase
 164   )
 165 {
 166   UINT64   StartTimeStamp;
 167
 168   // Initialize the platform specific controllers
 169   ArmPlatformInitialize (MpId);
 170
 171   if (ArmPlatformIsPrimaryCore (MpId) && PerformanceMeasurementEnabled ()) {
 172     // Initialize the Timer Library to setup the Timer HW controller
 173     TimerConstructor ();
 174     // We cannot call yet the PerformanceLib because the HOB List has not been initialized
 175     StartTimeStamp = GetPerformanceCounter ();
 176   } else {
 177     StartTimeStamp = 0;
 178   }
 179
 180   // Data Cache enabled on Primary core when MMU is enabled.
 181   ArmDisableDataCache ();
 182   // Invalidate instruction cache
 183   ArmInvalidateInstructionCache ();
 184   // Enable Instruction Caches on all cores.
 185   ArmEnableInstructionCache ();
 186
 187   // Define the Global Variable region when we are not running in XIP
 188   if (!IS_XIP()) {
 189     if (ArmPlatformIsPrimaryCore (MpId)) {
 190       if (ArmIsMpCore()) {
 191         // Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT)
 192         ArmCallSEV ();
 193       }
 194     } else {
 195       // Wait the Primary core has defined the address of the Global Variable region (event: ARM_CPU_EVENT_DEFAULT)
 196       ArmCallWFE ();
 197     }
 198   }
 199
 200   // If not primary Jump to Secondary Main
 201   if (ArmPlatformIsPrimaryCore (MpId)) {
 202
 203     InvalidateDataCacheRange ((VOID *)UefiMemoryBase,
 204                               FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));
 205
 206     // Goto primary Main.
 207     PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp);
 208   } else {
 209     SecondaryMain (MpId);
 210   }
 211
 212   // DXE Core should always load and never return
 213   ASSERT (FALSE);
 214 }