ArmPlatformPkg/PrePi/PrePi.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2017, ARM Limited. All rights reserved.
   4 *
   5 *  SPDX-License-Identifier: BSD-2-Clause-Patent
   6 *
   7 **/
   8
   9 #include <PiPei.h>
  10
  11 #include <Library/DebugAgentLib.h>
  12 #include <Library/PrePiLib.h>
  13 #include <Library/PrintLib.h>
  14 #include <Library/PrePiHobListPointerLib.h>
  15 #include <Library/TimerLib.h>
  16 #include <Library/PerformanceLib.h>
  17
  18 #include <Ppi/GuidedSectionExtraction.h>
  19 #include <Ppi/ArmMpCoreInfo.h>
  20 #include <Ppi/SecPerformance.h>
  21
  22 #include "PrePi.h"
  23
  24 #define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemoryEnd) || \
  25                   ((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= FixedPcdGet64 (PcdSystemMemoryBase)))
  26
  27 UINT64 mSystemMemoryEnd = FixedPcdGet64(PcdSystemMemoryBase) +
  28                           FixedPcdGet64(PcdSystemMemorySize) - 1;
  29
  30 EFI_STATUS
  31 GetPlatformPpi (
  32   IN  EFI_GUID  *PpiGuid,
  33   OUT VOID      **Ppi
  34   )
  35 {
  36   UINTN                   PpiListSize;
  37   UINTN                   PpiListCount;
  38   EFI_PEI_PPI_DESCRIPTOR  *PpiList;
  39   UINTN                   Index;
  40
  41   PpiListSize = 0;
  42   ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
  43   PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);
  44   for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
  45     if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {
  46       *Ppi = PpiList->Ppi;
  47       return EFI_SUCCESS;
  48     }
  49   }
  50
  51   return EFI_NOT_FOUND;
  52 }
  53
  54 VOID
  55 PrePiMain (
  56   IN  UINTN                     UefiMemoryBase,
  57   IN  UINTN                     StacksBase,
  58   IN  UINT64                    StartTimeStamp
  59   )
  60 {
  61   EFI_HOB_HANDOFF_INFO_TABLE*   HobList;
  62   ARM_MP_CORE_INFO_PPI*         ArmMpCoreInfoPpi;
  63   UINTN                         ArmCoreCount;
  64   ARM_CORE_INFO*                ArmCoreInfoTable;
  65   EFI_STATUS                    Status;
  66   CHAR8                         Buffer[100];
  67   UINTN                         CharCount;
  68   UINTN                         StacksSize;
  69   FIRMWARE_SEC_PERFORMANCE      Performance;
  70
  71   // If ensure the FD is either part of the System Memory or totally outside of the System Memory (XIP)
  72   ASSERT (IS_XIP() ||
  73           ((FixedPcdGet64 (PcdFdBaseAddress) >= FixedPcdGet64 (PcdSystemMemoryBase)) &&
  74            ((UINT64)(FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT64)mSystemMemoryEnd)));
  75
  76   // Initialize the architecture specific bits
  77   ArchInitialize ();
  78
  79   // Initialize the Serial Port
  80   SerialPortInitialize ();
  81   CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware (version %s built at %a on %a)\n\r",
  82     (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
  83   SerialPortWrite ((UINT8 *) Buffer, CharCount);
  84
  85   // Initialize the Debug Agent for Source Level Debugging
  86   InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
  87   SaveAndSetDebugTimerInterrupt (TRUE);
  88
  89   // Declare the PI/UEFI memory region
  90   HobList = HobConstructor (
  91     (VOID*)UefiMemoryBase,
  92     FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),
  93     (VOID*)UefiMemoryBase,
  94     (VOID*)StacksBase  // The top of the UEFI Memory is reserved for the stacks
  95     );
  96   PrePeiSetHobList (HobList);
  97
  98   // Initialize MMU and Memory HOBs (Resource Descriptor HOBs)
  99   Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));
 100   ASSERT_EFI_ERROR (Status);
 101
 102   // Create the Stacks HOB (reserve the memory for all stacks)
 103   if (ArmIsMpCore ()) {
 104     StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize) +
 105                  ((FixedPcdGet32 (PcdCoreCount) - 1) * FixedPcdGet32 (PcdCPUCoreSecondaryStackSize));
 106   } else {
 107     StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);
 108   }
 109   BuildStackHob (StacksBase, StacksSize);
 110
 111   //TODO: Call CpuPei as a library
 112   BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));
 113
 114   if (ArmIsMpCore ()) {
 115     // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid
 116     Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);
 117
 118     // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)
 119     ASSERT_EFI_ERROR (Status);
 120
 121     // Build the MP Core Info Table
 122     ArmCoreCount = 0;
 123     Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
 124     if (!EFI_ERROR(Status) && (ArmCoreCount > 0)) {
 125       // Build MPCore Info HOB
 126       BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);
 127     }
 128   }
 129
 130   // Store timer value logged at the beginning of firmware image execution
 131   Performance.ResetEnd = GetTimeInNanoSecond (StartTimeStamp);
 132
 133   // Build SEC Performance Data Hob
 134   BuildGuidDataHob (&gEfiFirmwarePerformanceGuid, &Performance, sizeof (Performance));
 135
 136   // Set the Boot Mode
 137   SetBootMode (ArmPlatformGetBootMode ());
 138
 139   // Initialize Platform HOBs (CpuHob and FvHob)
 140   Status = PlatformPeim ();
 141   ASSERT_EFI_ERROR (Status);
 142
 143   // Now, the HOB List has been initialized, we can register performance information
 144   PERF_START (NULL, "PEI", NULL, StartTimeStamp);
 145
 146   // SEC phase needs to run library constructors by hand.
 147   ProcessLibraryConstructorList ();
 148
 149   // Assume the FV that contains the SEC (our code) also contains a compressed FV.
 150   Status = DecompressFirstFv ();
 151   ASSERT_EFI_ERROR (Status);
 152
 153   // Load the DXE Core and transfer control to it
 154   Status = LoadDxeCoreFromFv (NULL, 0);
 155   ASSERT_EFI_ERROR (Status);
 156 }
 157
 158 VOID
 159 CEntryPoint (
 160   IN  UINTN                     MpId,
 161   IN  UINTN                     UefiMemoryBase,
 162   IN  UINTN                     StacksBase
 163   )
 164 {
 165   UINT64   StartTimeStamp;
 166
 167   // Initialize the platform specific controllers
 168   ArmPlatformInitialize (MpId);
 169
 170   if (ArmPlatformIsPrimaryCore (MpId) && PerformanceMeasurementEnabled ()) {
 171     // Initialize the Timer Library to setup the Timer HW controller
 172     TimerConstructor ();
 173     // We cannot call yet the PerformanceLib because the HOB List has not been initialized
 174     StartTimeStamp = GetPerformanceCounter ();
 175   } else {
 176     StartTimeStamp = 0;
 177   }
 178
 179   // Data Cache enabled on Primary core when MMU is enabled.
 180   ArmDisableDataCache ();
 181   // Invalidate Data cache
 182   ArmInvalidateDataCache ();
 183   // Invalidate instruction cache
 184   ArmInvalidateInstructionCache ();
 185   // Enable Instruction Caches on all cores.
 186   ArmEnableInstructionCache ();
 187
 188   // Define the Global Variable region when we are not running in XIP
 189   if (!IS_XIP()) {
 190     if (ArmPlatformIsPrimaryCore (MpId)) {
 191       if (ArmIsMpCore()) {
 192         // Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT)
 193         ArmCallSEV ();
 194       }
 195     } else {
 196       // Wait the Primary core has defined the address of the Global Variable region (event: ARM_CPU_EVENT_DEFAULT)
 197       ArmCallWFE ();
 198     }
 199   }
 200
 201   // If not primary Jump to Secondary Main
 202   if (ArmPlatformIsPrimaryCore (MpId)) {
 203     // Goto primary Main.
 204     PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp);
 205   } else {
 206     SecondaryMain (MpId);
 207   }
 208
 209   // DXE Core should always load and never return
 210   ASSERT (FALSE);
 211 }
 212