2 * Main file supporting the SEC Phase on ARM Platforms
4 * Copyright (c) 2011, ARM Limited. All rights reserved.
6 * This program and the accompanying materials
7 * are licensed and made available under the terms and conditions of the BSD License
8 * which accompanies this distribution. The full text of the license may be found at
9 * http://opensource.org/licenses/bsd-license.php
11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include <Library/DebugAgentLib.h>
17 #include <Library/PcdLib.h>
18 #include <Library/PrintLib.h>
19 #include <Library/BaseMemoryLib.h>
20 #include <Library/ArmLib.h>
21 #include <Library/SerialPortLib.h>
22 #include <Library/ArmPlatformLib.h>
23 #include <Library/ArmGicLib.h>
25 #include "SecInternal.h"
27 #define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);
29 extern VOID
*monitor_vector_table
;
40 // Primary CPU clears out the SCU tag RAMs, secondaries wait
41 if (IS_PRIMARY_CORE(MpId
)) {
42 if (FixedPcdGet32(PcdMPCoreSupport
)) {
46 // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
47 // In non SEC modules the init call is in autogenerated code.
48 SerialPortInitialize ();
51 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"UEFI firmware built at %a on %a\n\r",__TIME__
, __DATE__
);
52 SerialPortWrite ((UINT8
*) Buffer
, CharCount
);
54 // Initialize the Debug Agent for Source Level Debugging
55 InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC
, NULL
, NULL
);
56 SaveAndSetDebugTimerInterrupt (TRUE
);
58 // Now we've got UART, make the check:
59 // - The Vector table must be 32-byte aligned
60 ASSERT(((UINT32
)SecVectorTable
& ((1 << 5)-1)) == 0);
63 // Invalidate the data cache. Doesn't have to do the Data cache clean.
64 ArmInvalidateDataCache();
66 // Invalidate Instruction Cache
67 ArmInvalidateInstructionCache();
69 // Invalidate I & D TLBs
70 ArmInvalidateInstructionAndDataTlb();
72 // Enable Full Access to CoProcessors
73 ArmWriteCPACR (CPACR_CP_FULL_ACCESS
);
75 // Enable SWP instructions
76 ArmEnableSWPInstruction ();
78 // Enable program flow prediction, if supported.
79 ArmEnableBranchPrediction ();
81 if (FixedPcdGet32(PcdVFPEnabled
)) {
85 if (IS_PRIMARY_CORE(MpId
)) {
86 // Initialize peripherals that must be done at the early stage
87 // Example: Some L2x0 controllers must be initialized in Secure World
88 ArmPlatformSecInitialize ();
90 // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
91 // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
92 if (FeaturePcdGet(PcdSystemMemoryInitializeInSec
)) {
93 // Initialize system memory (DRAM)
94 ArmPlatformInitializeSystemMemory ();
97 // Some platform can change their physical memory mapping
98 ArmPlatformBootRemapping ();
101 // Test if Trustzone is supported on this platform
102 if (ArmPlatformTrustzoneSupported ()) {
103 // Ensure the Monitor Stack Base & Size have been set
104 ASSERT(PcdGet32(PcdCPUCoresSecMonStackBase
) != 0);
105 ASSERT(PcdGet32(PcdCPUCoreSecMonStackSize
) != 0);
107 if (FixedPcdGet32(PcdMPCoreSupport
)) {
108 // Setup SMP in Non Secure world
109 ArmSetupSmpNonSecure (GET_CORE_ID(MpId
));
112 // Enter Monitor Mode
113 enter_monitor_mode ((VOID
*)(PcdGet32(PcdCPUCoresSecMonStackBase
) + (PcdGet32(PcdCPUCoreSecMonStackSize
) * GET_CORE_POS(MpId
))));
115 //Write the monitor mode vector table address
116 ArmWriteVMBar((UINT32
) &monitor_vector_table
);
118 //-------------------- Monitor Mode ---------------------
119 // Setup the Trustzone Chipsets
120 if (IS_PRIMARY_CORE(MpId
)) {
121 ArmPlatformTrustzoneInit ();
123 // Wake up the secondary cores by sending a interrupt to everyone else
124 // NOTE 1: The Software Generated Interrupts are always enabled on Cortex-A9
125 // MPcore test chip on Versatile Express board, So the Software doesn't have to
126 // enable SGI's explicitly.
127 // 2: As no other Interrupts are enabled, doesn't have to worry about the priority.
128 // 3: As all the cores are in secure state, use secure SGI's
131 ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase
));
132 ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase
));
134 // Send SGI to all Secondary core to wake them up from WFI state.
135 ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase
), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE
, 0x0E);
137 // The secondary cores need to wait until the Trustzone chipsets configuration is done
138 // before switching to Non Secure World
140 // Enabled GIC CPU Interface
141 ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase
));
143 // Waiting for the SGI from the primary core
146 // Acknowledge the interrupt and send End of Interrupt signal.
147 ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase
), PRIMARY_CORE_ID
);
150 // Transfer the interrupt to Non-secure World
151 ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase
),PcdGet32(PcdGicInterruptInterfaceBase
));
153 // Write to CP15 Non-secure Access Control Register :
154 // - Enable CP10 and CP11 accesses in NS World
155 // - Enable Access to Preload Engine in NS World
156 // - Enable lockable TLB entries allocation in NS world
157 // - Enable R/W access to SMP bit of Auxiliary Control Register in NS world
158 ArmWriteNsacr (NSACR_NS_SMP
| NSACR_TL
| NSACR_PLE
| NSACR_CP(10) | NSACR_CP(11));
160 // CP15 Secure Configuration Register with Non Secure bit (SCR_NS), CPSR.A modified in any
161 // security state (SCR_AW), CPSR.F modified in any security state (SCR_FW)
162 ArmWriteScr (SCR_NS
| SCR_FW
| SCR_AW
);
164 if (IS_PRIMARY_CORE(MpId
)) {
165 SerialPrint ("Trust Zone Configuration is disabled\n\r");
168 // Trustzone is not enabled, just enable the Distributor and CPU interface
169 if (IS_PRIMARY_CORE(MpId
)) {
170 ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase
));
172 ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase
));
174 // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
175 // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
176 // Status Register as the the current one (CPSR).
177 copy_cpsr_into_spsr ();
180 JumpAddress
= PcdGet32 (PcdFvBaseAddress
);
181 ArmPlatformSecExtraAction (MpId
, &JumpAddress
);
183 return_from_exception (JumpAddress
);
184 //-------------------- Non Secure Mode ---------------------
186 // PEI Core should always load and never return
191 SecCommonExceptionEntry (
201 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"Reset Exception at 0x%X\n\r",LR
);
204 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"Undefined Exception at 0x%X\n\r",LR
);
207 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"SWI Exception at 0x%X\n\r",LR
);
210 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"PrefetchAbort Exception at 0x%X\n\r",LR
);
213 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"DataAbort Exception at 0x%X\n\r",LR
);
216 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"Reserved Exception at 0x%X\n\r",LR
);
219 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"IRQ Exception at 0x%X\n\r",LR
);
222 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"FIQ Exception at 0x%X\n\r",LR
);
225 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"Unknown Exception at 0x%X\n\r",LR
);
228 SerialPortWrite ((UINT8
*) Buffer
, CharCount
);