ArmPlatformPkg: Remove PcdStandalone from Sec module and Introduce ArmPlatformSecExtr...
[mirror_edk2.git] / ArmPlatformPkg / Sec / Sec.c
1 /** @file
2 * Main file supporting the SEC Phase for Versatile Express
3 *
4 * Copyright (c) 2011, ARM Limited. All rights reserved.
5 *
6 * This program and the accompanying materials
7 * are licensed and made available under the terms and conditions of the BSD License
8 * which accompanies this distribution. The full text of the license may be found at
9 * http://opensource.org/licenses/bsd-license.php
10 *
11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 *
14 **/
15
16 #include <Library/DebugLib.h>
17 #include <Library/DebugAgentLib.h>
18 #include <Library/PcdLib.h>
19 #include <Library/PrintLib.h>
20 #include <Library/BaseLib.h>
21 #include <Library/BaseMemoryLib.h>
22 #include <Library/ArmLib.h>
23 #include <Library/SerialPortLib.h>
24 #include <Library/ArmPlatformLib.h>
25
26 #include <Chipset/ArmV7.h>
27 #include <Drivers/PL390Gic.h>
28
29 #define ARM_PRIMARY_CORE 0
30
31 #define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);
32
33 extern VOID *monitor_vector_table;
34
35 VOID
36 ArmSetupGicNonSecure (
37 IN INTN GicDistributorBase,
38 IN INTN GicInterruptInterfaceBase
39 );
40
41 // Vector Table for Sec Phase
42 VOID
43 SecVectorTable (
44 VOID
45 );
46
47 VOID
48 NonSecureWaitForFirmware (
49 VOID
50 );
51
52 VOID
53 enter_monitor_mode(
54 IN VOID* Stack
55 );
56
57 VOID
58 return_from_exception (
59 IN UINTN NonSecureBase
60 );
61
62 VOID
63 copy_cpsr_into_spsr (
64 VOID
65 );
66
67 VOID
68 CEntryPoint (
69 IN UINTN CoreId
70 )
71 {
72 CHAR8 Buffer[100];
73 UINTN CharCount;
74 UINTN JumpAddress;
75
76 // Primary CPU clears out the SCU tag RAMs, secondaries wait
77 if (CoreId == ARM_PRIMARY_CORE) {
78 if (FixedPcdGet32(PcdMPCoreSupport)) {
79 ArmInvalidScu();
80 }
81
82 // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
83 // In non SEC modules the init call is in autogenerated code.
84 SerialPortInitialize ();
85
86 // Start talking
87 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware built at %a on %a\n\r",__TIME__, __DATE__);
88 SerialPortWrite ((UINT8 *) Buffer, CharCount);
89
90 // Initialize the Debug Agent for Source Level Debugging
91 InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);
92 SaveAndSetDebugTimerInterrupt (TRUE);
93
94 // Now we've got UART, make the check:
95 // - The Vector table must be 32-byte aligned
96 ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0);
97 }
98
99 // Invalidate the data cache. Doesn't have to do the Data cache clean.
100 ArmInvalidateDataCache();
101
102 //Invalidate Instruction Cache
103 ArmInvalidateInstructionCache();
104
105 //Invalidate I & D TLBs
106 ArmInvalidateInstructionAndDataTlb();
107
108 // Enable Full Access to CoProcessors
109 ArmWriteCPACR (CPACR_CP_FULL_ACCESS);
110
111 // Enable SWP instructions
112 ArmEnableSWPInstruction();
113
114 // Enable program flow prediction, if supported.
115 ArmEnableBranchPrediction();
116
117 if (FixedPcdGet32(PcdVFPEnabled)) {
118 ArmEnableVFP();
119 }
120
121 if (CoreId == ARM_PRIMARY_CORE) {
122 // Initialize peripherals that must be done at the early stage
123 // Example: Some L2x0 controllers must be initialized in Secure World
124 ArmPlatformSecInitialize ();
125
126 // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
127 // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
128 if (FeaturePcdGet(PcdSystemMemoryInitializeInSec)) {
129 // Initialize system memory (DRAM)
130 ArmPlatformInitializeSystemMemory ();
131 }
132
133 // Some platform can change their physical memory mapping
134 ArmPlatformBootRemapping ();
135 }
136
137 // Test if Trustzone is supported on this platform
138 if (ArmPlatformTrustzoneSupported()) {
139 if (FixedPcdGet32(PcdMPCoreSupport)) {
140 // Setup SMP in Non Secure world
141 ArmSetupSmpNonSecure (CoreId);
142 }
143
144 // Enter Monitor Mode
145 enter_monitor_mode((VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * CoreId)));
146
147 //Write the monitor mode vector table address
148 ArmWriteVMBar((UINT32) &monitor_vector_table);
149
150 //-------------------- Monitor Mode ---------------------
151 // Setup the Trustzone Chipsets
152 if (CoreId == ARM_PRIMARY_CORE) {
153 ArmPlatformTrustzoneInit();
154
155 // Wake up the secondary cores by sending a interrupt to everyone else
156 // NOTE 1: The Software Generated Interrupts are always enabled on Cortex-A9
157 // MPcore test chip on Versatile Express board, So the Software doesn't have to
158 // enable SGI's explicitly.
159 // 2: As no other Interrupts are enabled, doesn't have to worry about the priority.
160 // 3: As all the cores are in secure state, use secure SGI's
161 //
162
163 PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase));
164 PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
165
166 // Send SGI to all Secondary core to wake them up from WFI state.
167 PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
168 } else {
169 // The secondary cores need to wait until the Trustzone chipsets configuration is done
170 // before switching to Non Secure World
171
172 // Enabled GIC CPU Interface
173 PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
174
175 // Waiting for the SGI from the primary core
176 ArmCallWFI();
177
178 // Acknowledge the interrupt and send End of Interrupt signal.
179 PL390GicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);
180 }
181
182 // Transfer the interrupt to Non-secure World
183 PL390GicSetupNonSecure (PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase));
184
185 // Write to CP15 Non-secure Access Control Register :
186 // - Enable CP10 and CP11 accesses in NS World
187 // - Enable Access to Preload Engine in NS World
188 // - Enable lockable TLB entries allocation in NS world
189 // - Enable R/W access to SMP bit of Auxiliary Control Register in NS world
190 ArmWriteNsacr(NSACR_NS_SMP | NSACR_TL | NSACR_PLE | NSACR_CP(10) | NSACR_CP(11));
191
192 // CP15 Secure Configuration Register with Non Secure bit (SCR_NS), CPSR.A modified in any
193 // security state (SCR_AW), CPSR.F modified in any security state (SCR_FW)
194 ArmWriteScr(SCR_NS | SCR_FW | SCR_AW);
195 } else {
196 if (CoreId == ARM_PRIMARY_CORE) {
197 SerialPrint ("Trust Zone Configuration is disabled\n\r");
198 }
199
200 // Trustzone is not enabled, just enable the Distributor and CPU interface
201 if (CoreId == ARM_PRIMARY_CORE) {
202 PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase));
203 }
204 PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
205
206 // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
207 // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
208 // Status Register as the the current one (CPSR).
209 copy_cpsr_into_spsr ();
210 }
211
212 JumpAddress = PcdGet32 (PcdNormalFvBaseAddress);
213 ArmPlatformSecExtraAction (CoreId, &JumpAddress);
214
215 return_from_exception (JumpAddress);
216 //-------------------- Non Secure Mode ---------------------
217
218 // PEI Core should always load and never return
219 ASSERT (FALSE);
220 }
221
222 VOID
223 SecCommonExceptionEntry (
224 IN UINT32 Entry,
225 IN UINT32 LR
226 )
227 {
228 CHAR8 Buffer[100];
229 UINTN CharCount;
230
231 switch (Entry) {
232 case 0:
233 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR);
234 break;
235 case 1:
236 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR);
237 break;
238 case 2:
239 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR);
240 break;
241 case 3:
242 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR);
243 break;
244 case 4:
245 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR);
246 break;
247 case 5:
248 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR);
249 break;
250 case 6:
251 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR);
252 break;
253 case 7:
254 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR);
255 break;
256 default:
257 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR);
258 break;
259 }
260 SerialPortWrite ((UINT8 *) Buffer, CharCount);
261 while(1);
262 }