ArmPlatformPkg/Sec/Sec.c

   1 /** @file
   2 *  Main file supporting the SEC Phase on ARM Platforms
   3 *
   4 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   5 *
   6 *  This program and the accompanying materials
   7 *  are licensed and made available under the terms and conditions of the BSD License
   8 *  which accompanies this distribution.  The full text of the license may be found at
   9 *  http://opensource.org/licenses/bsd-license.php
  10 *
  11 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 *
  14 **/
  15
  16 #include <Library/DebugAgentLib.h>
  17 #include <Library/PrintLib.h>
  18 #include <Library/BaseMemoryLib.h>
  19 #include <Library/SerialPortLib.h>
  20 #include <Library/ArmGicLib.h>
  21 #include <Library/ArmCpuLib.h>
  22
  23 #include "SecInternal.h"
  24
  25 #define SerialPrint(txt)  SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);
  26
  27 extern VOID *monitor_vector_table;
  28
  29 VOID
  30 CEntryPoint (
  31   IN  UINTN                     MpId
  32   )
  33 {
  34   CHAR8           Buffer[100];
  35   UINTN           CharCount;
  36   UINTN           JumpAddress;
  37
  38   // Primary CPU clears out the SCU tag RAMs, secondaries wait
  39   if (IS_PRIMARY_CORE(MpId)) {
  40     ArmCpuSetup (MpId);
  41
  42     if (ArmIsMpCore()) {
  43       ArmCpuSynchronizeSignal (ARM_CPU_EVENT_BOOT_MEM_INIT);
  44     }
  45
  46     // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
  47     // In non SEC modules the init call is in autogenerated code.
  48     SerialPortInitialize ();
  49
  50     // Start talking
  51     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware built at %a on %a\n\r",__TIME__, __DATE__);
  52     SerialPortWrite ((UINT8 *) Buffer, CharCount);
  53
  54     // Initialize the Debug Agent for Source Level Debugging
  55     InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);
  56     SaveAndSetDebugTimerInterrupt (TRUE);
  57
  58     // Now we've got UART, make the check:
  59     // - The Vector table must be 32-byte aligned
  60     ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0);
  61
  62     // Enable the GIC distributor and CPU Interface
  63     // - no other Interrupts are enabled,  doesn't have to worry about the priority.
  64     // - all the cores are in secure state, use secure SGI's
  65     ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
  66     ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
  67   } else {
  68     // Enable the GIC CPU Interface
  69     ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
  70   }
  71
  72   // Invalidate the data cache. Doesn't have to do the Data cache clean.
  73   ArmInvalidateDataCache();
  74
  75   // Invalidate Instruction Cache
  76   ArmInvalidateInstructionCache();
  77
  78   // Invalidate I & D TLBs
  79   ArmInvalidateInstructionAndDataTlb();
  80
  81   // Enable Full Access to CoProcessors
  82   ArmWriteCPACR (CPACR_CP_FULL_ACCESS);
  83
  84   if (FixedPcdGet32 (PcdVFPEnabled)) {
  85     ArmEnableVFP();
  86   }
  87
  88   if (IS_PRIMARY_CORE(MpId)) {
  89     // Initialize peripherals that must be done at the early stage
  90     // Example: Some L2x0 controllers must be initialized in Secure World
  91     ArmPlatformSecInitialize ();
  92
  93     // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
  94     // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
  95     if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {
  96       // Initialize system memory (DRAM)
  97       ArmPlatformInitializeSystemMemory ();
  98     }
  99   }
 100
 101   // Test if Trustzone is supported on this platform
 102   if (FixedPcdGetBool (PcdTrustzoneSupport)) {
 103     // Ensure the Monitor Stack Base & Size have been set
 104     ASSERT(PcdGet32(PcdCPUCoresSecMonStackBase) != 0);
 105     ASSERT(PcdGet32(PcdCPUCoreSecMonStackSize) != 0);
 106
 107     if (ArmIsMpCore()) {
 108       // Setup SMP in Non Secure world
 109       ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId));
 110     }
 111
 112     // Enter Monitor Mode
 113     enter_monitor_mode ((VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * GET_CORE_POS(MpId))));
 114
 115     //Write the monitor mode vector table address
 116     ArmWriteVMBar((UINT32) &monitor_vector_table);
 117
 118     //-------------------- Monitor Mode ---------------------
 119     // Setup the Trustzone Chipsets
 120     if (IS_PRIMARY_CORE(MpId)) {
 121       ArmPlatformTrustzoneInit ();
 122
 123       // Waiting for the Primary Core to have finished to initialize the Secure World
 124       ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT);
 125     } else {
 126       // The secondary cores need to wait until the Trustzone chipsets configuration is done
 127       // before switching to Non Secure World
 128
 129       // Waiting for the Primary Core to have finished to initialize the Secure World
 130       ArmCpuSynchronizeWait (ARM_CPU_EVENT_SECURE_INIT);
 131     }
 132
 133     // Transfer the interrupt to Non-secure World
 134     ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
 135
 136     // Write to CP15 Non-secure Access Control Register
 137     ArmWriteNsacr (PcdGet32 (PcdArmNsacr));
 138
 139     // CP15 Secure Configuration Register
 140     ArmWriteScr (PcdGet32 (PcdArmScr));
 141   } else {
 142     if (IS_PRIMARY_CORE(MpId)) {
 143       SerialPrint ("Trust Zone Configuration is disabled\n\r");
 144     }
 145
 146     // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
 147     // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
 148     // Status Register as the the current one (CPSR).
 149     copy_cpsr_into_spsr ();
 150   }
 151
 152   JumpAddress = PcdGet32 (PcdFvBaseAddress);
 153   ArmPlatformSecExtraAction (MpId, &JumpAddress);
 154
 155   // If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition
 156   // By not set, the mode for Non Secure World is SVC
 157   if (PcdGet32 (PcdArmNonSecModeTransition) != 0) {
 158     set_non_secure_mode ((ARM_PROCESSOR_MODE)PcdGet32 (PcdArmNonSecModeTransition));
 159   }
 160
 161   return_from_exception (JumpAddress);
 162   //-------------------- Non Secure Mode ---------------------
 163
 164   // PEI Core should always load and never return
 165   ASSERT (FALSE);
 166 }
 167
 168 VOID
 169 SecCommonExceptionEntry (
 170   IN UINT32 Entry,
 171   IN UINT32 LR
 172   )
 173 {
 174   CHAR8           Buffer[100];
 175   UINTN           CharCount;
 176
 177   switch (Entry) {
 178   case 0:
 179     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR);
 180     break;
 181   case 1:
 182     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR);
 183     break;
 184   case 2:
 185     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR);
 186     break;
 187   case 3:
 188     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR);
 189     break;
 190   case 4:
 191     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR);
 192     break;
 193   case 5:
 194     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR);
 195     break;
 196   case 6:
 197     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR);
 198     break;
 199   case 7:
 200     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR);
 201     break;
 202   default:
 203     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR);
 204     break;
 205   }
 206   SerialPortWrite ((UINT8 *) Buffer, CharCount);
 207   while(1);
 208 }