2 * Main file supporting the SEC Phase for Versatile Express
4 * Copyright (c) 2011, ARM Limited. All rights reserved.
6 * This program and the accompanying materials
7 * are licensed and made available under the terms and conditions of the BSD License
8 * which accompanies this distribution. The full text of the license may be found at
9 * http://opensource.org/licenses/bsd-license.php
11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include <Library/DebugLib.h>
17 #include <Library/DebugAgentLib.h>
18 #include <Library/PcdLib.h>
19 #include <Library/PrintLib.h>
20 #include <Library/BaseLib.h>
21 #include <Library/BaseMemoryLib.h>
22 #include <Library/ArmLib.h>
23 #include <Library/SerialPortLib.h>
24 #include <Library/ArmPlatformLib.h>
26 #include <Chipset/ArmV7.h>
27 #include <Library/ArmGicLib.h>
29 #define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);
31 extern VOID
*monitor_vector_table
;
34 ArmSetupGicNonSecure (
35 IN INTN GicDistributorBase
,
36 IN INTN GicInterruptInterfaceBase
39 // Vector Table for Sec Phase
46 NonSecureWaitForFirmware (
56 return_from_exception (
57 IN UINTN NonSecureBase
74 // Primary CPU clears out the SCU tag RAMs, secondaries wait
75 if (IS_PRIMARY_CORE(MpId
)) {
76 if (FixedPcdGet32(PcdMPCoreSupport
)) {
80 // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
81 // In non SEC modules the init call is in autogenerated code.
82 SerialPortInitialize ();
85 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"UEFI firmware built at %a on %a\n\r",__TIME__
, __DATE__
);
86 SerialPortWrite ((UINT8
*) Buffer
, CharCount
);
88 // Initialize the Debug Agent for Source Level Debugging
89 InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC
, NULL
, NULL
);
90 SaveAndSetDebugTimerInterrupt (TRUE
);
92 // Now we've got UART, make the check:
93 // - The Vector table must be 32-byte aligned
94 ASSERT(((UINT32
)SecVectorTable
& ((1 << 5)-1)) == 0);
97 // Invalidate the data cache. Doesn't have to do the Data cache clean.
98 ArmInvalidateDataCache();
100 //Invalidate Instruction Cache
101 ArmInvalidateInstructionCache();
103 //Invalidate I & D TLBs
104 ArmInvalidateInstructionAndDataTlb();
106 // Enable Full Access to CoProcessors
107 ArmWriteCPACR (CPACR_CP_FULL_ACCESS
);
109 // Enable SWP instructions
110 ArmEnableSWPInstruction();
112 // Enable program flow prediction, if supported.
113 ArmEnableBranchPrediction();
115 if (FixedPcdGet32(PcdVFPEnabled
)) {
119 if (IS_PRIMARY_CORE(MpId
)) {
120 // Initialize peripherals that must be done at the early stage
121 // Example: Some L2x0 controllers must be initialized in Secure World
122 ArmPlatformSecInitialize ();
124 // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
125 // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
126 if (FeaturePcdGet(PcdSystemMemoryInitializeInSec
)) {
127 // Initialize system memory (DRAM)
128 ArmPlatformInitializeSystemMemory ();
131 // Some platform can change their physical memory mapping
132 ArmPlatformBootRemapping ();
135 // Test if Trustzone is supported on this platform
136 if (ArmPlatformTrustzoneSupported()) {
137 if (FixedPcdGet32(PcdMPCoreSupport
)) {
138 // Setup SMP in Non Secure world
139 ArmSetupSmpNonSecure (GET_CORE_ID(MpId
));
142 // Enter Monitor Mode
143 enter_monitor_mode ((VOID
*)(PcdGet32(PcdCPUCoresSecMonStackBase
) + (PcdGet32(PcdCPUCoreSecMonStackSize
) * GET_CORE_POS(MpId
))));
145 //Write the monitor mode vector table address
146 ArmWriteVMBar((UINT32
) &monitor_vector_table
);
148 //-------------------- Monitor Mode ---------------------
149 // Setup the Trustzone Chipsets
150 if (IS_PRIMARY_CORE(MpId
)) {
151 ArmPlatformTrustzoneInit();
153 // Wake up the secondary cores by sending a interrupt to everyone else
154 // NOTE 1: The Software Generated Interrupts are always enabled on Cortex-A9
155 // MPcore test chip on Versatile Express board, So the Software doesn't have to
156 // enable SGI's explicitly.
157 // 2: As no other Interrupts are enabled, doesn't have to worry about the priority.
158 // 3: As all the cores are in secure state, use secure SGI's
161 ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase
));
162 ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase
));
164 // Send SGI to all Secondary core to wake them up from WFI state.
165 ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase
), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE
, 0x0E);
167 // The secondary cores need to wait until the Trustzone chipsets configuration is done
168 // before switching to Non Secure World
170 // Enabled GIC CPU Interface
171 ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase
));
173 // Waiting for the SGI from the primary core
176 // Acknowledge the interrupt and send End of Interrupt signal.
177 ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase
), PRIMARY_CORE_ID
);
180 // Transfer the interrupt to Non-secure World
181 ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase
),PcdGet32(PcdGicInterruptInterfaceBase
));
183 // Write to CP15 Non-secure Access Control Register :
184 // - Enable CP10 and CP11 accesses in NS World
185 // - Enable Access to Preload Engine in NS World
186 // - Enable lockable TLB entries allocation in NS world
187 // - Enable R/W access to SMP bit of Auxiliary Control Register in NS world
188 ArmWriteNsacr(NSACR_NS_SMP
| NSACR_TL
| NSACR_PLE
| NSACR_CP(10) | NSACR_CP(11));
190 // CP15 Secure Configuration Register with Non Secure bit (SCR_NS), CPSR.A modified in any
191 // security state (SCR_AW), CPSR.F modified in any security state (SCR_FW)
192 ArmWriteScr(SCR_NS
| SCR_FW
| SCR_AW
);
194 if (IS_PRIMARY_CORE(MpId
)) {
195 SerialPrint ("Trust Zone Configuration is disabled\n\r");
198 // Trustzone is not enabled, just enable the Distributor and CPU interface
199 if (IS_PRIMARY_CORE(MpId
)) {
200 ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase
));
202 ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase
));
204 // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
205 // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
206 // Status Register as the the current one (CPSR).
207 copy_cpsr_into_spsr ();
210 JumpAddress
= PcdGet32 (PcdNormalFvBaseAddress
);
211 ArmPlatformSecExtraAction (MpId
, &JumpAddress
);
213 return_from_exception (JumpAddress
);
214 //-------------------- Non Secure Mode ---------------------
216 // PEI Core should always load and never return
221 SecCommonExceptionEntry (
231 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"Reset Exception at 0x%X\n\r",LR
);
234 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"Undefined Exception at 0x%X\n\r",LR
);
237 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"SWI Exception at 0x%X\n\r",LR
);
240 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"PrefetchAbort Exception at 0x%X\n\r",LR
);
243 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"DataAbort Exception at 0x%X\n\r",LR
);
246 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"Reserved Exception at 0x%X\n\r",LR
);
249 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"IRQ Exception at 0x%X\n\r",LR
);
252 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"FIQ Exception at 0x%X\n\r",LR
);
255 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"Unknown Exception at 0x%X\n\r",LR
);
258 SerialPortWrite ((UINT8
*) Buffer
, CharCount
);