ArmPlatformPkg/Sec/Sec.c

   1 /** @file
   2 *  Main file supporting the SEC Phase on ARM Platforms
   3 *
   4 *  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
   5 *
   6 *  This program and the accompanying materials
   7 *  are licensed and made available under the terms and conditions of the BSD License
   8 *  which accompanies this distribution.  The full text of the license may be found at
   9 *  http://opensource.org/licenses/bsd-license.php
  10 *
  11 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 *
  14 **/
  15
  16 #include <Library/ArmTrustedMonitorLib.h>
  17 #include <Library/DebugAgentLib.h>
  18 #include <Library/PrintLib.h>
  19 #include <Library/BaseMemoryLib.h>
  20 #include <Library/SerialPortLib.h>
  21 #include <Library/ArmGicLib.h>
  22 #include <Library/ArmCpuLib.h>
  23
  24 #include "SecInternal.h"
  25
  26 #define SerialPrint(txt)  SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);
  27
  28 VOID
  29 CEntryPoint (
  30   IN  UINTN                     MpId
  31   )
  32 {
  33   CHAR8           Buffer[100];
  34   UINTN           CharCount;
  35   UINTN           JumpAddress;
  36
  37   // Invalidate the data cache. Doesn't have to do the Data cache clean.
  38   ArmInvalidateDataCache();
  39
  40   // Invalidate Instruction Cache
  41   ArmInvalidateInstructionCache();
  42
  43   // Invalidate I & D TLBs
  44   ArmInvalidateInstructionAndDataTlb();
  45
  46   // CPU specific settings
  47   ArmCpuSetup (MpId);
  48
  49   // Enable Floating Point Coprocessor if supported by the platform
  50   if (FixedPcdGet32 (PcdVFPEnabled)) {
  51     ArmEnableVFP();
  52   }
  53
  54   // Primary CPU clears out the SCU tag RAMs, secondaries wait
  55   if (IS_PRIMARY_CORE(MpId)) {
  56     if (ArmIsMpCore()) {
  57       ArmCpuSynchronizeSignal (ARM_CPU_EVENT_BOOT_MEM_INIT);
  58     }
  59
  60     // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
  61     // In non SEC modules the init call is in autogenerated code.
  62     SerialPortInitialize ();
  63
  64     // Start talking
  65     if (FixedPcdGetBool (PcdTrustzoneSupport)) {
  66       CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Secure firmware (version %s built at %a on %a)\n\r",
  67           (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
  68     } else {
  69       CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Boot firmware (version %s built at %a on %a)\n\r",
  70           (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
  71     }
  72     SerialPortWrite ((UINT8 *) Buffer, CharCount);
  73
  74     // Initialize the Debug Agent for Source Level Debugging
  75     InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);
  76     SaveAndSetDebugTimerInterrupt (TRUE);
  77
  78     // Now we've got UART, make the check:
  79     // - The Vector table must be 32-byte aligned
  80     ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0);
  81
  82     // Enable the GIC distributor and CPU Interface
  83     // - no other Interrupts are enabled,  doesn't have to worry about the priority.
  84     // - all the cores are in secure state, use secure SGI's
  85     ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
  86     ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
  87   } else {
  88     // Enable the GIC CPU Interface
  89     ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
  90   }
  91
  92   // Enable Full Access to CoProcessors
  93   ArmWriteCPACR (CPACR_CP_FULL_ACCESS);
  94
  95   if (IS_PRIMARY_CORE(MpId)) {
  96     // Initialize peripherals that must be done at the early stage
  97     // Example: Some L2x0 controllers must be initialized in Secure World
  98     ArmPlatformSecInitialize ();
  99
 100     // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
 101     // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
 102     if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {
 103       // Initialize system memory (DRAM)
 104       ArmPlatformInitializeSystemMemory ();
 105     }
 106   }
 107
 108   // Test if Trustzone is supported on this platform
 109   if (FixedPcdGetBool (PcdTrustzoneSupport)) {
 110     if (ArmIsMpCore()) {
 111       // Setup SMP in Non Secure world
 112       ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId));
 113     }
 114
 115     // Either we use the Secure Stacks for Secure Monitor (in this case (Base == 0) && (Size == 0))
 116     // Or we use separate Secure Monitor stacks (but (Base != 0) && (Size != 0))
 117     ASSERT (((PcdGet32(PcdCPUCoresSecMonStackBase) == 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) == 0)) ||
 118             ((PcdGet32(PcdCPUCoresSecMonStackBase) != 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) != 0)));
 119
 120     // Enter Monitor Mode
 121     enter_monitor_mode ((UINTN)TrustedWorldInitialization, MpId, (VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * (GET_CORE_POS(MpId) + 1))));
 122   } else {
 123     if (IS_PRIMARY_CORE(MpId)) {
 124       SerialPrint ("Trust Zone Configuration is disabled\n\r");
 125     }
 126
 127     // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
 128     // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
 129     // Status Register as the the current one (CPSR).
 130     copy_cpsr_into_spsr ();
 131
 132     // Call the Platform specific function to execute additional actions if required
 133     JumpAddress = PcdGet32 (PcdFvBaseAddress);
 134     ArmPlatformSecExtraAction (MpId, &JumpAddress);
 135
 136     NonTrustedWorldTransition (MpId, JumpAddress);
 137   }
 138   ASSERT (0); // We must never return from the above function
 139 }
 140
 141 VOID
 142 TrustedWorldInitialization (
 143   IN  UINTN                     MpId
 144   )
 145 {
 146   UINTN   JumpAddress;
 147
 148   //-------------------- Monitor Mode ---------------------
 149
 150   // Set up Monitor World (Vector Table, etc)
 151   ArmSecureMonitorWorldInitialize ();
 152
 153   // Transfer the interrupt to Non-secure World
 154   ArmGicSetupNonSecure (MpId, PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
 155
 156   // Initialize platform specific security policy
 157   ArmPlatformTrustzoneInit (MpId);
 158
 159   // Setup the Trustzone Chipsets
 160   if (IS_PRIMARY_CORE(MpId)) {
 161     if (ArmIsMpCore()) {
 162       // Waiting for the Primary Core to have finished to initialize the Secure World
 163       ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT);
 164     }
 165   } else {
 166     // The secondary cores need to wait until the Trustzone chipsets configuration is done
 167     // before switching to Non Secure World
 168
 169     // Waiting for the Primary Core to have finished to initialize the Secure World
 170     ArmCpuSynchronizeWait (ARM_CPU_EVENT_SECURE_INIT);
 171   }
 172
 173   // Call the Platform specific fucntion to execute additional actions if required
 174   JumpAddress = PcdGet32 (PcdFvBaseAddress);
 175   ArmPlatformSecExtraAction (MpId, &JumpAddress);
 176
 177   // Write to CP15 Non-secure Access Control Register
 178   ArmWriteNsacr (PcdGet32 (PcdArmNsacr));
 179
 180   // CP15 Secure Configuration Register
 181   ArmWriteScr (PcdGet32 (PcdArmScr));
 182
 183   NonTrustedWorldTransition (MpId, JumpAddress);
 184 }
 185
 186 VOID
 187 NonTrustedWorldTransition (
 188   IN  UINTN                     MpId,
 189   IN  UINTN                     JumpAddress
 190   )
 191 {
 192   // If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition
 193   // By not set, the mode for Non Secure World is SVC
 194   if (PcdGet32 (PcdArmNonSecModeTransition) != 0) {
 195     set_non_secure_mode ((ARM_PROCESSOR_MODE)PcdGet32 (PcdArmNonSecModeTransition));
 196   }
 197
 198   return_from_exception (JumpAddress);
 199   //-------------------- Non Secure Mode ---------------------
 200
 201   // PEI Core should always load and never return
 202   ASSERT (FALSE);
 203 }
 204
 205 VOID
 206 SecCommonExceptionEntry (
 207   IN UINT32 Entry,
 208   IN UINT32 LR
 209   )
 210 {
 211   CHAR8           Buffer[100];
 212   UINTN           CharCount;
 213
 214   switch (Entry) {
 215   case 0:
 216     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR);
 217     break;
 218   case 1:
 219     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR);
 220     break;
 221   case 2:
 222     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR);
 223     break;
 224   case 3:
 225     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR);
 226     break;
 227   case 4:
 228     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR);
 229     break;
 230   case 5:
 231     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR);
 232     break;
 233   case 6:
 234     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR);
 235     break;
 236   case 7:
 237     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR);
 238     break;
 239   default:
 240     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR);
 241     break;
 242   }
 243   SerialPortWrite ((UINT8 *) Buffer, CharCount);
 244   while(1);
 245 }