2 // Copyright (c) 2011-2012, ARM Limited. All rights reserved.
4 // This program and the accompanying materials
5 // are licensed and made available under the terms and conditions of the BSD License
6 // which accompanies this distribution. The full text of the license may be found at
7 // http://opensource.org/licenses/bsd-license.php
9 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include <AsmMacroIoLib.h>
16 #include "SecInternal.h"
21 GCC_ASM_IMPORT(CEntryPoint)
22 GCC_ASM_IMPORT(ArmPlatformSecBootAction)
23 GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)
24 GCC_ASM_IMPORT(ArmDisableInterrupts)
25 GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
26 GCC_ASM_IMPORT(ArmWriteVBar)
27 GCC_ASM_IMPORT(ArmReadMpidr)
28 GCC_ASM_IMPORT(SecVectorTable)
29 GCC_ASM_IMPORT(ArmCallWFE)
30 GCC_ASM_EXPORT(_ModuleEntryPoint)
32 StartupAddr: .word ASM_PFX(CEntryPoint)
34 ASM_PFX(_ModuleEntryPoint):
35 // First ensure all interrupts are disabled
36 bl ASM_PFX(ArmDisableInterrupts)
38 // Ensure that the MMU and caches are off
39 bl ASM_PFX(ArmDisableCachesAndMmu)
41 // By default, we are doing a cold boot
42 mov r10, #ARM_SEC_COLD_BOOT
44 // Jump to Platform Specific Boot Action function
45 blx ASM_PFX(ArmPlatformSecBootAction)
47 // Set VBAR to the start of the exception vectors in Secure Mode
48 LoadConstantToReg (ASM_PFX(SecVectorTable), r0)
49 bl ASM_PFX(ArmWriteVBar)
53 bl ASM_PFX(ArmReadMpidr)
54 // Get ID of this CPU in Multicore system
55 LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
58 // Is it the Primary Core ?
59 LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)
61 // Only the primary core initialize the memory (SMC)
65 // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
66 // Otherwise we have to wait the Primary Core to finish the initialization
67 cmp r10, #ARM_SEC_COLD_BOOT
68 bne _SetupSecondaryCoreStack
70 // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)
71 bl ASM_PFX(ArmCallWFE)
72 // Now the Init Mem is initialized, we setup the secondary core stacks
73 b _SetupSecondaryCoreStack
76 // Initialize Init Boot Memory
77 bl ASM_PFX(ArmPlatformSecBootMemoryInit)
79 // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
80 LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)
82 _SetupPrimaryCoreStack:
83 // Get the top of the primary stacks (and the base of the secondary stacks)
84 LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
85 LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
88 LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)
90 // The reserved space for global variable must be 8-bytes aligned for pushing
91 // 64-bit variable on the stack
92 SetPrimaryStack (r1, r2, r3)
95 _SetupSecondaryCoreStack:
96 // Get the top of the primary stacks (and the base of the secondary stacks)
97 LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
98 LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
101 // Get the Core Position (ClusterId * 4) + CoreId
102 GetCorePositionFromMpId(r0, r5, r2)
103 // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
106 // StackOffset = CorePos * StackSize
107 LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)
109 // SP = StackBase + StackOffset
113 // Move sec startup address into a data register
114 // Ensure we're jumping to FV version of the code (not boot remapped alias)
117 // Jump to SEC C code