ArmPlatformPkg/Sec/SecEntryPoint.S

   1 //
   2 //  Copyright (c) 2011, ARM Limited. All rights reserved.
   3 //
   4 //  This program and the accompanying materials
   5 //  are licensed and made available under the terms and conditions of the BSD License
   6 //  which accompanies this distribution.  The full text of the license may be found at
   7 //  http://opensource.org/licenses/bsd-license.php
   8 //
   9 //  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 //  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 //
  12 //
  13
  14 #include <AutoGen.h>
  15 #include <AsmMacroIoLib.h>
  16 #include <Base.h>
  17 #include <Library/PcdLib.h>
  18 #include <Library/ArmPlatformLib.h>
  19
  20 .text
  21 .align 3
  22
  23 GCC_ASM_EXPORT(_ModuleEntryPoint)
  24
  25 GCC_ASM_IMPORT(CEntryPoint)
  26 GCC_ASM_IMPORT(ArmPlatformSecBootAction)
  27 GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)
  28 GCC_ASM_IMPORT(ArmDisableInterrupts)
  29 GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
  30 GCC_ASM_IMPORT(ArmWriteVBar)
  31 GCC_ASM_IMPORT(ArmReadMpidr)
  32 GCC_ASM_IMPORT(SecVectorTable)
  33
  34 #if (FixedPcdGet32(PcdMPCoreSupport))
  35 GCC_ASM_IMPORT(ArmIsScuEnable)
  36 #endif
  37
  38 StartupAddr:        .word       ASM_PFX(CEntryPoint)
  39 SecVectorTableAddr: .word       ASM_PFX(SecVectorTable)
  40
  41 ASM_PFX(_ModuleEntryPoint):
  42   // First ensure all interrupts are disabled
  43   bl    ASM_PFX(ArmDisableInterrupts)
  44
  45   // Ensure that the MMU and caches are off
  46   bl    ASM_PFX(ArmDisableCachesAndMmu)
  47
  48   // Jump to Platform Specific Boot Action function
  49   blx   ASM_PFX(ArmPlatformSecBootAction)
  50
  51   // Set VBAR to the start of the exception vectors in Secure Mode
  52   ldr   r0, =SecVectorTable
  53   bl    ASM_PFX(ArmWriteVBar)
  54
  55 _IdentifyCpu:
  56   // Identify CPU ID
  57   bl    ASM_PFX(ArmReadMpidr)
  58   // Get ID of this CPU in Multicore system
  59   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
  60   and   r5, r0, r1
  61
  62   // Is it the Primary Core ?
  63   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)
  64   cmp   r5, r1
  65   // Only the primary core initialize the memory (SMC)
  66   beq   _InitMem
  67
  68 #if (FixedPcdGet32(PcdMPCoreSupport))
  69   // ... The secondary cores wait for SCU to be enabled
  70 _WaitForEnabledScu:
  71   bl    ASM_PFX(ArmIsScuEnable)
  72   tst   r1, #1
  73   beq   _WaitForEnabledScu
  74   b     _SetupSecondaryCoreStack
  75 #endif
  76
  77 _InitMem:
  78   // Initialize Init Boot Memory
  79   bl    ASM_PFX(ArmPlatformInitializeBootMemory)
  80
  81   // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
  82   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)
  83
  84 _SetupPrimaryCoreStack:
  85   LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r2)
  86   LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r3)
  87   // Calculate the Top of the Stack
  88   add   r2, r2, r3
  89   LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r3)
  90
  91   // The reserved space for global variable must be 8-bytes aligned for pushing
  92   // 64-bit variable on the stack
  93   SetPrimaryStack (r2, r3, r1)
  94
  95   // Set all the SEC global variables to 0
  96   mov     r3, sp
  97   mov     r1, #0x0
  98 _InitGlobals:
  99   str     r1, [r3], #4
 100   cmp     r3, r2
 101   blt     _InitGlobals
 102
 103   b     _PrepareArguments
 104
 105 _SetupSecondaryCoreStack:
 106   // Get the Core Position (ClusterId * 4) + CoreId
 107   GetCorePositionInStack(r0, r5, r1)
 108   // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
 109   add   r0, r0, #1
 110
 111   // Get the base of the stack for the secondary cores
 112   LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
 113   LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
 114   add   r1, r1, r2
 115
 116   // StackOffset = CorePos * StackSize
 117   mul   r0, r0, r2
 118   // SP = StackBase + StackOffset
 119   add   sp, r1, r0
 120
 121
 122 _PrepareArguments:
 123   // Move sec startup address into a data register
 124   // Ensure we're jumping to FV version of the code (not boot remapped alias)
 125   ldr   r3, StartupAddr
 126
 127   // Jump to SEC C code
 128   //    r0 = mp_id
 129   mov   r0, r5
 130   blx   r3
 131
 132 _NeverReturn:
 133   b _NeverReturn