ArmPlatformPkg/Sec/SecEntryPoint.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # ARM VE Entry point. Reset vector in FV header will brach to
   4 # _ModuleEntryPoint.
   5 #
   6 #  Copyright (c) 2011, ARM Limited. All rights reserved.
   7 #
   8 #  This program and the accompanying materials
   9 #  are licensed and made available under the terms and conditions of the BSD License
  10 #  which accompanies this distribution.  The full text of the license may be found at
  11 #  http://opensource.org/licenses/bsd-license.php
  12 #
  13 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  14 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  15 #
  16 #------------------------------------------------------------------------------
  17
  18 #include <AsmMacroIoLib.h>
  19 #include <Base.h>
  20 #include <Library/PcdLib.h>
  21 #include <Library/ArmPlatformLib.h>
  22 #include <AutoGen.h>
  23
  24 #Start of Code section
  25 .text
  26 .align 3
  27
  28 #make _ModuleEntryPoint as global
  29 GCC_ASM_EXPORT(_ModuleEntryPoint)
  30
  31 #global functions referenced by this module
  32 GCC_ASM_IMPORT(CEntryPoint)
  33 GCC_ASM_IMPORT(ArmPlatformIsMemoryInitialized)
  34 GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)
  35 GCC_ASM_IMPORT(ArmDisableInterrupts)
  36 GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
  37 GCC_ASM_IMPORT(ArmWriteVBar)
  38 GCC_ASM_IMPORT(ArmReadMpidr)
  39 GCC_ASM_IMPORT(SecVectorTable)
  40
  41 #if (FixedPcdGet32(PcdMPCoreSupport))
  42 GCC_ASM_IMPORT(ArmIsScuEnable)
  43 #endif
  44
  45 StartupAddr:        .word   ASM_PFX(CEntryPoint)
  46 SecVectorTableAddr: .word               ASM_PFX(SecVectorTable)
  47
  48 ASM_PFX(_ModuleEntryPoint):
  49  #Set VBAR to the start of the exception vectors in Secure Mode
  50   ldr   r0, SecVectorTableAddr
  51   bl   ASM_PFX(ArmWriteVBar)
  52
  53   # First ensure all interrupts are disabled
  54   bl   ASM_PFX(ArmDisableInterrupts)
  55
  56   # Ensure that the MMU and caches are off
  57   bl  ASM_PFX(ArmDisableCachesAndMmu)
  58
  59 _IdentifyCpu:
  60   # Identify CPU ID
  61   bl    ASM_PFX(ArmReadMpidr)
  62   // Get ID of this CPU in Multicore system
  63   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
  64   and   r5, r0, r1
  65
  66   #get ID of this CPU in Multicore system
  67   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)
  68   cmp   r5, r1
  69   # Only the primary core initialize the memory (SMC)
  70   beq   _InitMem
  71
  72 #if (FixedPcdGet32(PcdMPCoreSupport))
  73   # ... The secondary cores wait for SCU to be enabled
  74 _WaitForEnabledScu:
  75   bl    ASM_PFX(ArmIsScuEnable)
  76   tst   r1, #1
  77   beq   _WaitForEnabledScu
  78   b     _SetupStack
  79 #endif
  80
  81 _InitMem:
  82   bl    ASM_PFX(ArmPlatformIsMemoryInitialized)
  83   bne   _SetupStack
  84
  85   # Initialize Init Memory
  86   bl    ASM_PFX(ArmPlatformInitializeBootMemory)
  87
  88   # Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
  89   mov   r5, #0
  90
  91 _SetupStack:
  92   # Setup Stack for the 4 CPU cores
  93   #Read Stack Base address from PCD
  94   LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
  95
  96   #read Stack size from PCD
  97   LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize), r2)
  98
  99   #calcuate Stack Pointer reg value using Stack size and CPU ID.
 100   mov     r3,r5         @ r3 = core_id
 101   mul     r3,r3,r2      @ r3 = core_id * stack_size = offset from the stack base
 102   add     r3,r3,r1      @ r3 ldr= stack_base + offset
 103   mov     sp, r3
 104
 105   # move sec startup address into a data register
 106   # ensure we're jumping to FV version of the code (not boot remapped alias)
 107   ldr   r3, StartupAddr
 108
 109   # Move the CoreId in r0 to be the first argument of the SEC Entry Point
 110   mov   r0, r5
 111
 112   # jump to SEC C code
 113   #    r0 = core_id
 114   blx  r3
 115
 116