ArmPlatformPkg/Sec/SecEntryPoint.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # ARM VE Entry point. Reset vector in FV header will brach to
   4 # _ModuleEntryPoint.
   5 #
   6 #  Copyright (c) 2011, ARM Limited. All rights reserved.
   7 #
   8 #  This program and the accompanying materials
   9 #  are licensed and made available under the terms and conditions of the BSD License
  10 #  which accompanies this distribution.  The full text of the license may be found at
  11 #  http://opensource.org/licenses/bsd-license.php
  12 #
  13 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  14 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  15 #
  16 #------------------------------------------------------------------------------
  17
  18 #include <AsmMacroIoLib.h>
  19 #include <Base.h>
  20 #include <Library/PcdLib.h>
  21 #include <Library/ArmPlatformLib.h>
  22 #include <AutoGen.h>
  23
  24 #Start of Code section
  25 .text
  26 .align 3
  27
  28 #make _ModuleEntryPoint as global
  29 GCC_ASM_EXPORT(_ModuleEntryPoint)
  30
  31 #global functions referenced by this module
  32 GCC_ASM_IMPORT(CEntryPoint)
  33 GCC_ASM_IMPORT(ArmPlatformSecBootAction)
  34 GCC_ASM_IMPORT(ArmPlatformIsMemoryInitialized)
  35 GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)
  36 GCC_ASM_IMPORT(ArmDisableInterrupts)
  37 GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
  38 GCC_ASM_IMPORT(ArmWriteVBar)
  39 GCC_ASM_IMPORT(ArmReadMpidr)
  40 GCC_ASM_IMPORT(SecVectorTable)
  41
  42 #if (FixedPcdGet32(PcdMPCoreSupport))
  43 GCC_ASM_IMPORT(ArmIsScuEnable)
  44 #endif
  45
  46 StartupAddr:        .word   ASM_PFX(CEntryPoint)
  47 SecVectorTableAddr: .word               ASM_PFX(SecVectorTable)
  48
  49 ASM_PFX(_ModuleEntryPoint):
  50   # First ensure all interrupts are disabled
  51   bl   ASM_PFX(ArmDisableInterrupts)
  52
  53   # Ensure that the MMU and caches are off
  54   bl  ASM_PFX(ArmDisableCachesAndMmu)
  55
  56   # Jump to Platform Specific Boot Action function
  57   blx   ASM_PFX(ArmPlatformSecBootAction)
  58
  59   # Set VBAR to the start of the exception vectors in Secure Mode
  60   ldr   r0, =SecVectorTable
  61   bl    ASM_PFX(ArmWriteVBar)
  62
  63 _IdentifyCpu:
  64   # Identify CPU ID
  65   bl    ASM_PFX(ArmReadMpidr)
  66   // Get ID of this CPU in Multicore system
  67   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
  68   and   r5, r0, r1
  69
  70   #get ID of this CPU in Multicore system
  71   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)
  72   cmp   r5, r1
  73   # Only the primary core initialize the memory (SMC)
  74   beq   _InitMem
  75
  76 #if (FixedPcdGet32(PcdMPCoreSupport))
  77   # ... The secondary cores wait for SCU to be enabled
  78 _WaitForEnabledScu:
  79   bl    ASM_PFX(ArmIsScuEnable)
  80   tst   r1, #1
  81   beq   _WaitForEnabledScu
  82   b     _SetupStack
  83 #endif
  84
  85 _InitMem:
  86   bl    ASM_PFX(ArmPlatformIsMemoryInitialized)
  87   bne   _SetupStack
  88
  89   # Initialize Init Memory
  90   bl    ASM_PFX(ArmPlatformInitializeBootMemory)
  91
  92   # Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
  93   mov   r5, #0
  94
  95 _SetupStack:
  96   # Setup Stack for the 4 CPU cores
  97   #Read Stack Base address from PCD
  98   LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
  99
 100   #read Stack size from PCD
 101   LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize), r2)
 102
 103   #calcuate Stack Pointer reg value using Stack size and CPU ID.
 104   mov     r3,r5         @ r3 = core_id
 105   mul     r3,r3,r2      @ r3 = core_id * stack_size = offset from the stack base
 106   add     r3,r3,r1      @ r3 ldr= stack_base + offset
 107   mov     sp, r3
 108
 109   # move sec startup address into a data register
 110   # ensure we're jumping to FV version of the code (not boot remapped alias)
 111   ldr   r3, StartupAddr
 112
 113   # Move the CoreId in r0 to be the first argument of the SEC Entry Point
 114   mov   r0, r5
 115
 116   # jump to SEC C code
 117   #    r0 = core_id
 118   blx  r3
 119
 120