1 #------------------------------------------------------------------------------
3 # ARM VE Entry point. Reset vector in FV header will brach to
6 # Copyright (c) 2011, ARM Limited. All rights reserved.
8 # This program and the accompanying materials
9 # are licensed and made available under the terms and conditions of the BSD License
10 # which accompanies this distribution. The full text of the license may be found at
11 # http://opensource.org/licenses/bsd-license.php
13 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #------------------------------------------------------------------------------
18 #include <AsmMacroIoLib.h>
20 #include <Library/PcdLib.h>
21 #include <Library/ArmPlatformLib.h>
24 #Start of Code section
28 #make _ModuleEntryPoint as global
29 GCC_ASM_EXPORT(_ModuleEntryPoint)
31 #global functions referenced by this module
32 GCC_ASM_IMPORT(CEntryPoint)
33 GCC_ASM_IMPORT(ArmPlatformIsMemoryInitialized)
34 GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)
35 GCC_ASM_IMPORT(ArmDisableInterrupts)
36 GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
37 GCC_ASM_IMPORT(ArmWriteVBar)
38 GCC_ASM_IMPORT(SecVectorTable)
40 #if (FixedPcdGet32(PcdMPCoreSupport))
41 GCC_ASM_IMPORT(ArmIsScuEnable)
44 StartupAddr: .word CEntryPoint
45 SecVectorTableAddr: .word SecVectorTable
47 ASM_PFX(_ModuleEntryPoint):
48 #Set VBAR to the start of the exception vectors in Secure Mode
49 ldr r0, SecVectorTableAddr
50 bl ASM_PFX(ArmWriteVBar)
52 # First ensure all interrupts are disabled
53 bl ASM_PFX(ArmDisableInterrupts)
55 # Ensure that the MMU and caches are off
56 bl ASM_PFX(ArmDisableCachesAndMmu)
60 bl ASM_PFX(ArmReadMpidr)
63 #get ID of this CPU in Multicore system
65 # Only the primary core initialize the memory (SMC)
68 #if (FixedPcdGet32(PcdMPCoreSupport))
69 # ... The secondary cores wait for SCU to be enabled
71 bl ASM_PFX(ArmIsScuEnable)
73 beq _WaitForEnabledScu
78 bl ASM_PFX(ArmPlatformIsMemoryInitialized)
81 # Initialize Init Memory
82 bl ASM_PFX(ArmPlatformInitializeBootMemory)
84 # Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
88 # Setup Stack for the 4 CPU cores
89 #Read Stack Base address from PCD
90 LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase) ,r1)
92 #read Stack size from PCD
93 LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize) ,r2)
95 #calcuate Stack Pointer reg value using Stack size and CPU ID.
96 mov r3,r5 @ r3 = core_id
97 mul r3,r3,r2 @ r3 = core_id * stack_size = offset from the stack base
98 add r3,r3,r1 @ r3 ldr= stack_base + offset
101 # move sec startup address into a data register
102 # ensure we're jumping to FV version of the code (not boot remapped alias)
105 # Move the CoreId in r0 to be the first argument of the SEC Entry Point