ArmPlatformPkg/Sec/SecEntryPoint.asm

   1 //
   2 //  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
   3 //
   4 //  This program and the accompanying materials
   5 //  are licensed and made available under the terms and conditions of the BSD License
   6 //  which accompanies this distribution.  The full text of the license may be found at
   7 //  http://opensource.org/licenses/bsd-license.php
   8 //
   9 //  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 //  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 //
  12 //
  13
  14 #include <AutoGen.h>
  15 #include <AsmMacroIoLib.h>
  16 #include "SecInternal.h"
  17
  18   INCLUDE AsmMacroIoLib.inc
  19
  20   IMPORT  CEntryPoint
  21   IMPORT  ArmPlatformSecBootAction
  22   IMPORT  ArmPlatformSecBootMemoryInit
  23   IMPORT  ArmDisableInterrupts
  24   IMPORT  ArmDisableCachesAndMmu
  25   IMPORT  ArmWriteVBar
  26   IMPORT  ArmReadMpidr
  27   IMPORT  ArmCallWFE
  28   IMPORT  SecVectorTable
  29   EXPORT  _ModuleEntryPoint
  30
  31   PRESERVE8
  32   AREA    SecEntryPoint, CODE, READONLY
  33
  34 StartupAddr        DCD      CEntryPoint
  35
  36 _ModuleEntryPoint FUNCTION
  37   // First ensure all interrupts are disabled
  38   blx   ArmDisableInterrupts
  39
  40   // Ensure that the MMU and caches are off
  41   blx   ArmDisableCachesAndMmu
  42
  43   // By default, we are doing a cold boot
  44   mov   r10, #ARM_SEC_COLD_BOOT
  45
  46   // Jump to Platform Specific Boot Action function
  47   blx   ArmPlatformSecBootAction
  48
  49   // Set VBAR to the start of the exception vectors in Secure Mode
  50   ldr   r0, =SecVectorTable
  51   blx   ArmWriteVBar
  52
  53 _IdentifyCpu
  54   // Identify CPU ID
  55   bl    ArmReadMpidr
  56   // Get ID of this CPU in Multicore system
  57   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
  58   and   r5, r0, r1
  59
  60   // Is it the Primary Core ?
  61   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)
  62   cmp   r5, r3
  63   // Only the primary core initialize the memory (SMC)
  64   beq   _InitMem
  65
  66 _WaitInitMem
  67   // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
  68   // Otherwise we have to wait the Primary Core to finish the initialization
  69   cmp   r10, #ARM_SEC_COLD_BOOT
  70   bne   _SetupSecondaryCoreStack
  71
  72   // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)
  73   bl    ArmCallWFE
  74   // Now the Init Mem is initialized, we setup the secondary core stacks
  75   b     _SetupSecondaryCoreStack
  76
  77 _InitMem
  78   // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
  79   cmp   r10, #ARM_SEC_COLD_BOOT
  80   bne   _SetupPrimaryCoreStack
  81
  82   // Initialize Init Boot Memory
  83   bl    ArmPlatformSecBootMemoryInit
  84
  85   // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
  86   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)
  87
  88 _SetupPrimaryCoreStack
  89   // Get the top of the primary stacks (and the base of the secondary stacks)
  90   LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
  91   LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
  92   add   r1, r1, r2
  93
  94   LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)
  95
  96   // The reserved space for global variable must be 8-bytes aligned for pushing
  97   // 64-bit variable on the stack
  98   SetPrimaryStack (r1, r2, r3)
  99   b     _PrepareArguments
 100
 101 _SetupSecondaryCoreStack
 102   // Get the top of the primary stacks (and the base of the secondary stacks)
 103   LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
 104   LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
 105   add   r1, r1, r2
 106
 107   // Get the Core Position (ClusterId * 4) + CoreId
 108   GetCorePositionFromMpId(r0, r5, r2)
 109   // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
 110   add   r0, r0, #1
 111
 112   // StackOffset = CorePos * StackSize
 113   LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)
 114   mul   r0, r0, r2
 115   // SP = StackBase + StackOffset
 116   add   sp, r1, r0
 117
 118 _PrepareArguments
 119   // Move sec startup address into a data register
 120   // Ensure we're jumping to FV version of the code (not boot remapped alias)
 121   ldr   r3, StartupAddr
 122
 123   // Jump to SEC C code
 124   //    r0 = mp_id
 125   //    r1 = Boot Mode
 126   mov   r0, r5
 127   mov   r1, r10
 128   blx   r3
 129   ENDFUNC
 130
 131 _NeverReturn
 132   b _NeverReturn
 133   END