ArmPlatformPkg/Sec/SecEntryPoint.asm

   1 //
   2 //  Copyright (c) 2011, ARM Limited. All rights reserved.
   3 //
   4 //  This program and the accompanying materials
   5 //  are licensed and made available under the terms and conditions of the BSD License
   6 //  which accompanies this distribution.  The full text of the license may be found at
   7 //  http://opensource.org/licenses/bsd-license.php
   8 //
   9 //  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 //  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 //
  12 //
  13
  14 #include <AutoGen.h>
  15 #include <AsmMacroIoLib.h>
  16 #include <Base.h>
  17 #include <Library/PcdLib.h>
  18 #include <Library/ArmPlatformLib.h>
  19
  20   INCLUDE AsmMacroIoLib.inc
  21
  22   IMPORT  CEntryPoint
  23   IMPORT  ArmPlatformIsMemoryInitialized
  24   IMPORT  ArmPlatformInitializeBootMemory
  25   IMPORT  ArmDisableInterrupts
  26   IMPORT  ArmDisableCachesAndMmu
  27   IMPORT  ArmWriteVBar
  28   IMPORT  ArmReadMpidr
  29   IMPORT  SecVectorTable
  30   EXPORT  _ModuleEntryPoint
  31
  32 #if (FixedPcdGet32(PcdMPCoreSupport))
  33   IMPORT  ArmIsScuEnable
  34 #endif
  35
  36   PRESERVE8
  37   AREA    SecEntryPoint, CODE, READONLY
  38
  39 StartupAddr        DCD      CEntryPoint
  40
  41 _ModuleEntryPoint
  42   //Set VBAR to the start of the exception vectors in Secure Mode
  43   ldr   r0, =SecVectorTable
  44   blx   ArmWriteVBar
  45
  46   // First ensure all interrupts are disabled
  47   blx   ArmDisableInterrupts
  48
  49   // Ensure that the MMU and caches are off
  50   blx   ArmDisableCachesAndMmu
  51
  52 _IdentifyCpu
  53   // Identify CPU ID
  54   bl    ArmReadMpidr
  55   // Get ID of this CPU in Multicore system
  56   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
  57   and   r5, r0, r1
  58
  59   // Is it the Primary Core ?
  60   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)
  61   cmp   r5, r1
  62   // Only the primary core initialize the memory (SMC)
  63   beq   _InitMem
  64
  65 #if (FixedPcdGet32(PcdMPCoreSupport))
  66   // ... The secondary cores wait for SCU to be enabled
  67 _WaitForEnabledScu
  68   bl    ArmIsScuEnable
  69   tst   r1, #1
  70   beq   _WaitForEnabledScu
  71   b     _SetupStack
  72 #endif
  73
  74 _InitMem
  75   bl    ArmPlatformIsMemoryInitialized
  76   bne   _SetupStack
  77
  78   // Initialize Init Memory
  79   bl    ArmPlatformInitializeBootMemory
  80
  81   // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
  82   mov   r5, #0
  83
  84 _SetupStack
  85   // Setup Stack for the 4 CPU cores
  86   //Read Stack Base address from PCD
  87   LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
  88
  89   // Read Stack size from PCD
  90   LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize), r2)
  91
  92   // Calcuate Stack Pointer reg value using Stack size and CPU ID.
  93   mov     r3,r5         // r3 = core_id
  94   mul     r3,r3,r2      // r3 = core_id * stack_size = offset from the stack base
  95   add     r3,r3,r1      // r3 = stack_base + offset
  96   mov     sp, r3
  97
  98   // Move sec startup address into a data register
  99   // ensure we're jumping to FV version of the code (not boot remapped alias)
 100   ldr   r3, StartupAddr
 101
 102   // Jump to SEC C code
 103   //    r0 = mp_id
 104   mov   r0, r5
 105   blx   r3
 106
 107   END